📄 pcidrv.c
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* @desc Register Overlay Structure for PARAMENTRY.
* ============================================================================
*/
typedef struct DM64LCPCI_paramEntry_tags {
volatile Uint32 OPTION ;
volatile Uint32 SRC ;
volatile Uint32 A_B_CNT ;
volatile Uint32 DST ;
volatile Uint32 SRC_DST_BIDX ;
volatile Uint32 LINK_BCNTRLD ;
volatile Uint32 SRC_DST_CIDX ;
volatile Uint32 CCNT ;
} DM64LCPCI_paramEntry ;
/** ============================================================================
* @name DM64LCPCI_edmaRegs
*
* @desc Register Overlay Structure for EDMA.
* ============================================================================
*/
typedef struct DM64LCPCI_edmaRegs_tag {
volatile Uint32 REV ;
volatile Uint32 CCCFG ;
volatile Uint8 RSVD0 [248] ;
volatile Uint32 DCHMAP [64] ;
volatile Uint32 QCHMAP [8] ;
volatile Uint8 RSVD1 [32] ;
volatile Uint32 DMAQNUM [8] ;
volatile Uint32 QDMAQNUM ;
volatile Uint8 RSVD2 [28] ;
volatile Uint32 QUETCMAP ;
volatile Uint32 QUEPRI ;
volatile Uint8 RSVD3 [120] ;
volatile Uint32 EMR ;
volatile Uint32 EMRH ;
volatile Uint32 EMCR ;
volatile Uint32 EMCRH ;
volatile Uint32 QEMR ;
volatile Uint32 QEMCR ;
volatile Uint32 CCERR ;
volatile Uint32 CCERRCLR ;
volatile Uint32 EEVAL ;
volatile Uint8 RSVD4 [28] ;
volatile Uint8 RSVD5 [64] ;
volatile Uint32 QRAE [8] ;
volatile Uint8 RSVD6[96] ;
volatile Uint8 RSVD7 [512] ;
volatile Uint32 QSTAT [8] ;
volatile Uint32 QWMTHRA ;
volatile Uint32 QWMTHRB ;
volatile Uint8 RSVD8 [24] ;
volatile Uint32 CCSTAT ;
volatile Uint8 RSVD9 [188] ;
volatile Uint32 AETCTL ;
volatile Uint32 AETSTAT ;
volatile Uint32 AETCMD ;
volatile Uint8 RSVD10 [244] ;
volatile Uint32 MPFAR ;
volatile Uint32 MPFSR ;
volatile Uint32 MPFCR ;
volatile Uint32 MPPAG ;
volatile Uint32 MPPA [8] ;
volatile Uint8 RSVD11 [2000] ;
volatile Uint32 ER ;
volatile Uint32 ERH ;
volatile Uint32 ECR ;
volatile Uint32 ECRH ;
volatile Uint32 ESR ;
volatile Uint32 ESRH ;
volatile Uint32 CER ;
volatile Uint32 CERH ;
volatile Uint32 EER ;
volatile Uint32 EERH ;
volatile Uint32 EECR ;
volatile Uint32 EECRH ;
volatile Uint32 EESR ;
volatile Uint32 EESRH ;
volatile Uint32 SER ;
volatile Uint32 SERH ;
volatile Uint32 SECR ;
volatile Uint32 SECRH ;
volatile Uint8 RSVD12 [8] ;
volatile Uint32 IER ;
volatile Uint32 IERH ;
volatile Uint32 IECR ;
volatile Uint32 IECRH ;
volatile Uint32 IESR ;
volatile Uint32 IESRH ;
volatile Uint32 IPR ;
volatile Uint32 IPRH ;
volatile Uint32 ICR ;
volatile Uint32 ICRH ;
volatile Uint32 IEVAL ;
volatile Uint8 RSVD13 [4] ;
volatile Uint32 QER ;
volatile Uint32 QEER ;
volatile Uint32 QEECR ;
volatile Uint32 QEESR ;
volatile Uint32 QSER ;
volatile Uint32 QSECR ;
volatile Uint8 RSVD14 [3944] ;
volatile Uint8 RSVD15 [4096] ;
volatile Uint8 RSVD16 [4096] ;
DM64LCPCI_paramEntry PARAMENTRY[512] ;
} DM64LCPCI_edmaRegs ;
/** ============================================================================
* @name DM64LCPCI_pciRegs
*
* @desc PCI Back end register overlay structure.
* ============================================================================
*/
typedef struct DM64LCPCI_pciRegs_tag {
volatile Uint32 PCIREVID ;
volatile Uint8 RSVD0 [12] ;
volatile Uint32 PCISTATSET ;
volatile Uint32 PCISTATCLR ;
volatile Uint8 RSVD1 [8] ;
volatile Uint32 PCIHINTSET ;
volatile Uint32 PCIHINTCLR ;
volatile Uint8 RSVD2 [8] ;
volatile Uint32 PCIBINTSET ;
volatile Uint32 PCIBINTCLR ;
volatile Uint32 PCIBCLKMGT ;
volatile Uint8 RSVD3 [196] ;
volatile Uint32 PCIVENDEVMIR ;
volatile Uint32 PCICSRMIR ;
volatile Uint32 PCICLREVMIR ;
volatile Uint32 PCICLINEMIR ;
volatile Uint32 PCIBAR0MSK ;
volatile Uint32 PCIBAR1MSK ;
volatile Uint32 PCIBAR2MSK ;
volatile Uint32 PCIBAR3MSK ;
volatile Uint32 PCIBAR4MSK ;
volatile Uint32 PCIBAR5MSK ;
volatile Uint8 RSVD4[4] ;
volatile Uint32 PCISUBIDMIR ;
volatile Uint8 RSVD5 [4] ;
volatile Uint32 PCICPBPTRMIR ;
volatile Uint8 RSVD6 [4] ;
volatile Uint32 PCILGINTMIR ;
volatile Uint8 RSVD7 [64] ;
volatile Uint32 PCISLVCNTL ;
volatile Uint8 RSVD8 [60] ;
volatile Uint32 PCIBAR0TRL ;
volatile Uint32 PCIBAR1TRL ;
volatile Uint32 PCIBAR2TRL ;
volatile Uint32 PCIBAR3TRL ;
volatile Uint32 PCIBAR4TRL ;
volatile Uint32 PCIBAR5TRL ;
volatile Uint8 RSVD9 [8] ;
volatile Uint32 PCIBARMIR [6] ;
volatile Uint8 RSVD10 [264] ;
volatile Uint32 PCIMCFGDAT ;
volatile Uint32 PCIMCFGADR ;
volatile Uint32 PCIMCFGCMD ;
volatile Uint8 RSVD11 [4] ;
volatile Uint32 PCIMSTCFG ;
volatile Uint32 PCIADDSUB [32] ;
volatile Uint32 PCIVENDEVPRG ;
volatile Uint32 PCICMDSTATPRG ;
volatile Uint32 PCICLREVPRG ;
volatile Uint32 PCISUBIDPRG ;
volatile Uint32 PCIMAXLGPRG ;
volatile Uint32 PCILRSTREG ;
volatile Uint32 PCICFGDONE ;
volatile Uint32 PCIBAR0MPRG ;
volatile Uint32 PCIBAR1MPRG ;
volatile Uint32 PCIBAR2MPRG ;
volatile Uint32 PCIBAR3MPRG ;
volatile Uint32 PCIBAR4MPRG ;
volatile Uint32 PCIBAR5MPRG ;
volatile Uint32 PCIBAR0PRG ;
volatile Uint32 PCIBAR1PRG ;
volatile Uint32 PCIBAR2PRG ;
volatile Uint32 PCIBAR3PRG ;
volatile Uint32 PCIBAR4PRG ;
volatile Uint32 PCIBAR5PRG ;
volatile Uint32 PCIBAR0TRLPRG ;
volatile Uint32 PCIBAR1TRLPRG ;
volatile Uint32 PCIBAR2TRLPRG ;
volatile Uint32 PCIBAR3TRLPRG ;
volatile Uint32 PCIBAR4TRLPRG ;
volatile Uint32 PCIBAR5TRLPRG ;
volatile Uint32 PCIBASENPRG ;
} DM64LCPCI_pciRegs ;
struct pci_dev * GEM = NULL ;
Uint32 regBase = 0 ;
Uint32 memBase = 0 ;
Uint32 ddrRegBase = 0 ;
Uint32 * regVirt = NULL ;
Uint32 * memVirt = NULL ;
Uint32 * ddrRegVirt = NULL ;
Uint32 memLen = 0 ;
Uint32 regLen = 0 ;
Uint32 ddrRegLen = 0 ;
/* ============================================================================
* @func PCI_FindPciDevices
*
* @desc This function locates DM642 PCI cards on system.
*
* @modif None.
* ============================================================================
*/
Void
PCI_FindPciDevices (Void)
{
struct pci_dev * dev = NULL ;
while ((dev = pci_find_device (PCI_TI_VENDOR, PCI_TI_DEVICE, dev)) != NULL)
{
GEM = dev ;
break ;
}
}
/* ============================================================================
* @func PCI_readBAR
*
* @desc This function reads config.
*
* @modif None.
* ============================================================================
*/
Void PCI_readBAR (Void)
{
Uint32 barStart [3] ;
Uint32 barLen [3] ;
Uint32 barFlags [3] ;
barStart [0] = pci_resource_start (GEM, 0);
barLen [0] = pci_resource_len (GEM, 0);
barFlags [0] = pci_resource_flags (GEM, 0);
barStart [1] = pci_resource_start (GEM, 1);
barLen [1] = pci_resource_len (GEM, 1);
barFlags [1] = pci_resource_flags (GEM, 1);
barStart [2] = pci_resource_start (GEM, 2);
barLen [2] = pci_resource_len (GEM, 2);
barFlags [2] = pci_resource_flags (GEM, 2);
/* ---------------------------------------------------------------------
* Map the L2RAM memory region
* ---------------------------------------------------------------------
*/
if (barFlags [0] & IORESOURCE_MEM) {
memBase = barStart [0] ;
/* Map the memory region. */
request_mem_region (memBase,
barLen [0],
"DSPLINK");
}
else {
/* Map the memory region. */
request_region (memBase,
barLen [0],
"DSPLINK");
}
if (memBase > 0) {
memVirt = ioremap (barStart [0],
barLen [0]) ;
}
/* ---------------------------------------------------------------------
* Map the DDR REG memory region
* ---------------------------------------------------------------------
*/
if (barFlags [1] & IORESOURCE_MEM) {
ddrRegBase = barStart [1] ;
/* Map the memory region. */
request_mem_region (ddrRegBase,
barLen [1],
"DSPLINK");
}
else {
/* Map the memory region. */
request_region (ddrRegBase,
barLen [1],
"DSPLINK");
}
if (ddrRegBase > 0) {
ddrRegVirt = ioremap (barStart [1],
barLen [1]) ;
}
/* ---------------------------------------------------------------------
* Map the REG memory region
* ---------------------------------------------------------------------
*/
if (barFlags [2] & IORESOURCE_MEM) {
regBase = barStart [2] ;
/* Map the memory region. */
request_mem_region (regBase,
barLen [2],
"DSPLINK");
}
else {
/* Map the memory region. */
request_region (regBase,
barLen [2],
"DSPLINK");
}
if (regBase > 0) {
regVirt = ioremap (barStart [2],
barLen [2]) ;
}
memLen = barLen [0] ;
ddrRegLen = barLen [1] ;
regLen = barLen [2] ;
}
/* =============================================================================
* @func PCI_setMaster
*
* @desc This function makes the given device to be master.
*
* @modif None.
* ============================================================================
*/
Void
PCI_setMaster (void)
{
Int32 retVal ;
Uint16 cmdVal ;
struct pci_dev * dev ;
dev = GEM ;
/* set the DMA mask */
if (pci_set_dma_mask (dev, 0xfffffff0ULL)) {
}
/*
* set the desired PCI dev to be master, this internally sets the latency
* timer.
*/
pci_set_master (dev) ;
pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x80);
/* Add support memory write invalidate */
retVal = pci_set_mwi (dev) ;
pci_read_config_word (dev, PCI_COMMAND, (u16 *) &cmdVal) ;
/* and set the master bit in command register. */
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