psp_pci_bios_sample_main.c

DM6437评估版BIOS下的PCI驱动程序

    }
    /*
     * De-initialize the PCI driver and hardware
     */
    deInitPCI(pciHandle);
    PCI_DEBUG("PCI Test completed successfully\n");
}



void pciCallback(Uint32 interruptMask,Ptr appData)
{
    if(NULL     !=  appData)
    {
        appData =   appData;
        interruptMask    =    interruptMask;
    }
    /*
     * Clear the status all the interrupts
     */
    pciRegs->PCISTATCLR    |=    pciRegs->PCISTATCLR;
    interruptCalled    =    TRUE;
}
/**
 *  \brief Initialize the PCI driver and hardware
 *
 *  This function does the initialization of PCI controller and PCI
 *  driver. This function is deviced for DM6437/C6424 PCI driver. This function
 *  will change if the PCI controller or PCI device changes.
 *
 *  \return hPci Handle to PCI driver
 */
Ptr initPCI()
{
    PAL_Result status = PAL_SOK;
    Ptr hPci = NULL;
    PAL_sysPciInitConfig    pciParams;

    /* Power up settings for PCI
     * PCIDAT = 0: VDD3P3V_PWDN - bit -13
     */
    sysCtlRegs->VDD3P3V_PWDN &=  (0xFFFFDFFFu);

    /* PINMUX settings for PCI */
    /* HOSTBK = 0: and GIOBK = 0 Bit 7:4 = 000*/
    sysCtlRegs->PINMUX1 &=  (~(0xF0));
    sysCtlRegs->PINMUX1 |=  (0x1);
    /* AEM = 0 or 5 and PCIEN = 1 for enabling PCI */
    sysCtlRegs->PINMUX0 &=  ~(0x7);

    /* Create PCI driver instance */
    status =    PAL_sysPCICreate(PCI_CONTROLLER_INSTANCE, NULL);
    if(PAL_SOK  !=  status)
    {
        PCI_DEBUG("ERROR: Creation of PCI driver instance failed\r\n");
        return NULL;
    }
    /* Pass application callback as NULL and application data as NULL */
    pciParams.appCb     =   &pciCallback;
    pciParams.appData   =   NULL;
    /* Open driver instance */
    hPci    =   (Ptr)PAL_sysPCIOpen(PCI_CONTROLLER_INSTANCE, &pciParams);
    if(NULL ==  hPci)
    {
        PCI_DEBUG("ERROR: Opening PCI driver failed\r\n");
        return NULL;
    }
    return hPci;
}
/**
 *  \brief De-initialize PCI driver
 *
 *  This function de-initializes the PCI driver. This function is deviced for DM6437/C6424
 *  PCI driver. This function will change if the PCI controller or PCI device changes.
 *
 *  \param  hPci [IN]       Handle to PCI driver
 *  \return None
 */
void deInitPCI(Ptr hPci)
{
    PAL_sysPCIClose((PSP_Handle)hPci, NULL);
    PAL_sysPCIDelete(PCI_CONTROLLER_INSTANCE);
}
/**
*  \brief Read data from PCI devices attached to the PCI bus
 *
 *  This function will read data from PCI devices attached to the PCI bus.
 *  Source address, destination address, number of bytes to be read and transfer
 *  mode have to be passed to this API. This function is deviced for DM6437/C6424
 *  PCI driver. This function will change if the PCI controller or PCI device changes.
 *
 *  \param  hPci      [IN]      Handle to PCI driver
 *  \param  srcAddr   [IN]      Source adddress
 *  \param  dstAddr   [IN]      Destination adddress
 *  \param  readCount [IN]      Number of bytes to read
 *  \param  xfrMode   [IN]      Options for read operation

 *  \return If successful, 0
 *          If failed, returns negative number - IOM Error code
 */
Int32 readData(Ptr hPci, Uint8* srcAddr, Uint8* dstAddr, Uint32 readCount)
{
    Uint32  masterConfig    =   0;
    PAL_Result status = PAL_SOK;

    Uint32 tmpSrcAddr = 0;
    Int32 i = 0;

    /* Get the master control */
    status  =    PAL_sysPCIGetMemMapReg(hPci,
                                        PAL_SYSPCI_MIRROR_CMD_STATUS_REG,
                                        PAL_SYS_PCI_READ_WRITE_SIZE_WORD,
                                        &masterConfig);
    if(PAL_SOK  !=  status)
    {
        PCI_DEBUG("ERROR: Unable to read the Memory mapped configuration register\r\n");
        return status;
    }
    /*
     * Enable bus master bit
     */
    masterConfig    |=  0x00000004;
    status  =    PAL_sysPCISetMemMapReg(hPci,
                                        PAL_SYSPCI_MIRROR_CMD_STATUS_REG,
                                        PAL_SYS_PCI_READ_WRITE_SIZE_WORD,
                                        masterConfig);
    if(PAL_SOK  !=  status)
    {
        PCI_DEBUG("ERROR: Unable to write the memory mapped configuration register\r\n");
        return status;
    }
    /*
     * Set the DSP translation register
     */
    status = PAL_sysPCISetMemMapReg(   hPci,
                                                        PAL_SYSPCI_ADDR_SUBSTITUTION_REG0,
                                                        PAL_SYS_PCI_READ_WRITE_SIZE_WORD,
                                                        (Uint32)srcAddr);
    if(PAL_SOK  !=  status)
    {
        PCI_DEBUG("ERROR: Unable to write the DSP to PCI translation register\r\n");
        return status;
    }

    /* Update PCI Register for Address Sub   */
    tmpSrcAddr = PAL_SYS_PCI_TO_DSP_MEM_MAP_ADDR(srcAddr );

    BCACHE_inv((Ptr)dstAddr, readCount, 1);

    for(i = 0; i< readCount; i+=4)
    {
        *((Uint32 *)dstAddr) = *((Uint32 *)tmpSrcAddr);
        tmpSrcAddr+=4;
        dstAddr+=4;
    }

    return PAL_SOK;
}
/**
 *  \brief Write data onto PCI devices attached to the PCI bus
 *
 *  This function will write data on PCI devices attached to the PCI bus.
 *  Source address, destination address, number of bytes to be written and transfer
 *  mode have to be passed to this API. This function is deviced for DM6437/C6424
 *  PCI driver. This function will change if the PCI controller or PCI device changes.
 *
 *  \param  hPci      [IN]      Handle to PCI driver
 *  \param  srcAddr   [IN]      Source adddress
 *  \param  dstAddr   [IN]      Destination adddress
 *  \param  readCount [IN]      Number of bytes to read
 *  \param  xfrMode   [IN]      Options for read operation

 *  \return If successful, 0
 *          If failed, returns negative number - IOM Error code
 */
Int32 writeData(Ptr hPci,Uint8* srcAddr, Uint8* dstAddr, Uint32 writeCount)
{
    Uint32  masterConfig    =   0;
    PAL_Result status = PAL_SOK;
    Uint32 pageBase = 0;
    Uint32 tmpDstAddr = 0;
    Int32 i = 0;

    /* Get the master control */
    status  =    PAL_sysPCIGetMemMapReg(hPci,
                                        PAL_SYSPCI_MIRROR_CMD_STATUS_REG,
                                        PAL_SYS_PCI_READ_WRITE_SIZE_WORD,
                                        &masterConfig);
    if(PAL_SOK  !=  status)
    {
        PCI_DEBUG("ERROR: Unable to read the memory mapped configuration register\r\n");
        return status;
    }
    /* Enable bus master bit */
    masterConfig    |=  0x00000004;
    status  =    PAL_sysPCISetMemMapReg(hPci,
                                        PAL_SYSPCI_MIRROR_CMD_STATUS_REG,
                                        PAL_SYS_PCI_READ_WRITE_SIZE_WORD,
                                        masterConfig);
    if(PAL_SOK  !=  status)
    {
        PCI_DEBUG("ERROR: Unable to write the memory mapped configuration register\r\n");
        return status;
    }

    /*
     * Program the pagebase address
     */
    pageBase = (Uint32) dstAddr & 0xFF800000;
    status = PAL_sysPCISetMemMapReg(   hPci,
                                                        PAL_SYSPCI_ADDR_SUBSTITUTION_REG0,
                                                        PAL_SYS_PCI_READ_WRITE_SIZE_WORD,
                                                        pageBase);
    if(PAL_SOK  !=  status)
    {
        PCI_DEBUG("ERROR: Unable to write the DSP to PCI translation register\r\n");
        return status;
    }

    /* Update PCI Register for Address Sub */

    tmpDstAddr = PAL_SYS_PCI_TO_DSP_MEM_MAP_ADDR(dstAddr);

    for(i = 0; i< writeCount; i+=4)
    {
        *((Uint32 *)tmpDstAddr) = *((Uint32 *)srcAddr);
        tmpDstAddr+=4;
        srcAddr+=4;
    }

    BCACHE_wb ((Ptr)tmpDstAddr, writeCount, 1);

    return PAL_SOK;
}

void generateHostInterrupt()
{
    Uint32 interruptStatus = 0;
    PAL_Result    status    = 0;

    if(NULL != pciHandle)
    {
            /*
             * Read the status set register
             */
            status  =    PAL_sysPCIGetMemMapReg(pciHandle,
                                            PAL_SYSPCI_STATUS_SET,
                                            PAL_SYS_PCI_READ_WRITE_SIZE_WORD,
                                            &interruptStatus);
             if(PAL_SOK  !=  status)
             {
                 PCI_DEBUG("ERROR: Unable to write the memory mapped configuration register while interrupt genration\n");
                 return;
             }

            /*
             * Set DSPINT bit in memory mapped status set register
             */
            interruptStatus    =    interruptStatus | TRIGGER_DSPINT_MASK;
            /*
             * Write the status set register to trigger interrupt
             */
            status  =    PAL_sysPCISetMemMapReg(pciHandle,
                                        PAL_SYSPCI_STATUS_SET,
                                        PAL_SYS_PCI_READ_WRITE_SIZE_WORD,
                                        interruptStatus);
             if(PAL_SOK  !=  status)
             {
                 PCI_DEBUG("ERROR: Unable to write the Backend configuration register while interrupt genration\n");
                 return;
             }

    }
}