adder3bit.v

来自「一位全加器」· Verilog 代码 · 共 13 行

module  Adder3Bit  (First, Second, Carry_In,Sum_Out, Carry_Out);
	input  [2:0]   First, Second;
	input  Carry_In;
	output  [2:0]  Sum_Out;
	output   Carry_Out ;
	wire [1:0]   Car_temp ;
	//通过例化1位加法形成3位加法器
  //module   Adder1Bit  (A, B, Cin, Sum, Cout) ;
Adder1Bit   A1 (.A (First[0]), .B(Second[0]), .Cin (Carry_In),.Sum (Sum_Out[0]), .Cout(Car_temp[0]) );
Adder1Bit   A2 (.A(First[1]), .B(Second[1]), .Cin(Car_temp[0]),.Sum(Sum_Out [ 1 ]),.Cout(Car_temp[1]) ) ;
Adder1Bit   A3 (.A(First[2]),.B(Second[2]), .Cin(Car_temp[1]),.Sum( Sum_Out [2]), .Cout(Carry_Out)) ;
endmodule