dch1.rpt

it is used to understand the basic working of a BCH encoder/Decoder

----- Date             : Thu Nov 27 12:35:16 1997
----- Module Name      : DCH1
----- Library Name     : X3000
----- Output Directory : .
----- Operating Voltage: 5.000000
----- Operating Temp   : 25
----- Process          : TYPICAL
----- Logic Type       : LARGE
----- area/speed Factor: 1.000000
----- Package          : DEFAULT

             *********************************************
                             Output Drives
             *********************************************


   Output            Drive              Output             Drive
----------------------------------------------------------------------------
                    rise     fall                         rise     fall
                   ----------------                      ----------------
DOUT[0]            0.0000   0.0000    DOUT[1]            0.0000   0.0000 
DOUT[2]            0.0000   0.0000    DOUT[3]            0.0000   0.0000 


             *********************************************
                             Input Loadings
             *********************************************


       Input             Load        Input             Load
-------------------------------------------------------------------
      CLK                4.000      PE                 5.000  
      DIN[0]             1.000      DIN[1]             1.000  
      DIN[2]             1.000      DIN[3]             1.000  



             *********************************************
                             Timing Report
             *********************************************


   Output          Delay            Required       Required Load   External Cap
-----------------------------------------------------------------------------
                  rise     fall      rise     fall      (Buffering)  (Timing)
                ----------------   --------------    ------------  ----------
DIN__CH__[0]      3.00     3.00     <none>   <none>         1.0       1.0
DIN__CH__[1]      3.00     3.00     <none>   <none>         1.0       1.0
DIN__CH__[2]      3.00     3.00     <none>   <none>         1.0       1.0
DIN__CH__[3]      3.00     3.00     <none>   <none>         1.0       1.0
DOUT[0]           1.00     1.00     <none>   <none>         2.0       2.0
DOUT[1]           1.00     1.00     <none>   <none>         2.0       2.0
DOUT[2]           1.00     1.00     <none>   <none>         2.0       2.0
DOUT[3]           1.00     1.00     <none>   <none>         3.0       3.0
----------------------------------------------------------------------------
Total Delta          0.00      0.00
Max.  Delay          3.00      3.00
Min.  Delay          1.00      1.00

               ****************************************
                       Critical Path Delays
               ****************************************


 Node             Arrival      Required     Slack        Type
 -----------------------------------------------------------------------
DIN__CH__[0]       3.00            -           -          X3000:OR2:1
NET_$8             2.00            -           -          X3000:AND2:2
NET_$9             1.00            -           -          X3000:INV:I
PE Primary Input

DIN__CH__[0]       3.00            -           -          X3000:OR2:1
NET_$8             2.00            -           -          X3000:AND2:2
NET_$9             1.00            -           -          X3000:INV:I
PE Primary Input

DIN__CH__[1]       3.00            -           -          X3000:OR2:1
NET_$6             2.00            -           -          X3000:AND2:1
SGEN_NODE_4        1.00            -           -          X3000:XOR2:1
CH_12_$Q   R/B/LC Output

DIN__CH__[1]       3.00            -           -          X3000:OR2:1
NET_$6             2.00            -           -          X3000:AND2:1
SGEN_NODE_4        1.00            -           -          X3000:XOR2:1
CH_12_$Q   R/B/LC Output

DIN__CH__[2]       3.00            -           -          X3000:OR2:1
NET_$4             2.00            -           -          X3000:AND2:2
NET_$9             1.00            -           -          X3000:INV:I
PE Primary Input

DIN__CH__[2]       3.00            -           -          X3000:OR2:1
NET_$4             2.00            -           -          X3000:AND2:2
NET_$9             1.00            -           -          X3000:INV:I
PE Primary Input

DIN__CH__[3]       3.00            -           -          X3000:OR2:1
NET_$2             2.00            -           -          X3000:AND2:2
NET_$9             1.00            -           -          X3000:INV:I
PE Primary Input

DIN__CH__[3]       3.00            -           -          X3000:OR2:1
NET_$2             2.00            -           -          X3000:AND2:2
NET_$9             1.00            -           -          X3000:INV:I
PE Primary Input


 R/B/LC => Register/BlackBox/LibraryComponent 



             *********************************************
                          Gate Usage Summary
             *********************************************


Cell         Count       Area/Cell    Cell         Count       Area/Cell
----------------------------------------------------------------------------
MX3000:FD       4           0.00      X3000:AND2      8           0.25
X3000:INV       1           0.00      X3000:OR2       4           0.25
X3000:XOR2      1           0.25      
----------------------------------------------------------------------------

Total Cells :          18             Total Area  :        3.25


             *********************************************
                           Netlist Statistics
             *********************************************

Maximum level of gates =       3    Total number of nets   =      24
Maximum pins per net   =       6    Average pins per net   =    2.62
Maximum load per net   =    5.00    Average load per net   =    1.62