dec.vhd

it is used to understand the basic working of a BCH encoder/Decoder

	SIGNAL l, lin, lcarry, lxor, lcomp: BIT_VECTOR(0 TO sizel-1);
	SIGNAL lce: BIT;
  BEGIN
	dout<= lcomp(sizel-1);
	-- compare --> lcomp(sizel-1)<= (cb>=l)
	lcomp(0)<= NOT l(0) OR cb(0);
	gencomp:
	FOR i IN 1 TO sizel-1 GENERATE
	  lcomp(i)<= (lcomp(i-1) AND (NOT l(i) OR cb(i)))  OR  (NOT l(i) AND cb(i));
	END GENERATE;

	-- register l substractor; lin<= 2*cb-l+1 <=> { lin<=2*cb+2+NOT(l) }
	lin(0)<= NOT l(0);
	lin(1) <= cb(0) XOR l(1);
	lcarry(1)<= cb(0) OR NOT l(1);
	      genl:
	FOR i IN 2 TO sizel-1 GENERATE
		lxor(i)<= cb(i-1) XOR NOT l(i);
		lin(i)<= lxor(i) XOR lcarry(i-1);
		lcarry(i)<= (NOT l(i) AND cb(i-1)) OR (lxor(i) AND lcarry(i-1));
	END GENERATE;
	lce<= ce AND bsel;
  PROCESS BEGIN  
	WAIT UNTIL clk'EVENT AND clk='1';
	-- l register 
	IF reset='1' THEN
		l(0)<= bsel;   -- if Syn1=0 l<= 0, else l<=1
	ELSIF lce='1' THEN
		l(0)<= lin(0);
	END IF;

	FOR i IN 1 TO sizel-1 LOOP
	  IF reset='1' THEN
		l(i)<= '0';
	  ELSIF lce='1' THEN
		l(i)<= lin(i);
	  END IF;
	END LOOP;
  END PROCESS;
END dcla;

-------------------------------------------------------------------------------	
-- control system and counter

	USE WORK.const.ALL;
ENTITY dcount IS
PORT (clk, reset, drnzero: IN BIT;
	bsel, bufCe, bufkCe, chpe, msmpe, snce, synpe, vdout, vdout1,c0first, cce, caLast1, cbBeg, dringPe, cei: OUT BIT);
		-- vdout - delaied by one clock vdout11
END dcount;

ARCHITECTURE dcounta OF dcount IS
	COMPONENT drd1ce -- single register with clock enable
		PORT ( clk, ce, din: IN BIT; dout: OUT BIT);
		END COMPONENT; 
	  	FOR ALL: drd1ce USE ENTITY WORK.drd1ce (drd1cea);
	COMPONENT dca  -- counter a
		PORT (clk, reset: IN BIT; cRes: OUT BIT;
		dout: OUT BIT_VECTOR(0 TO sizea-1));	
		END COMPONENT; 
	  	FOR ALL: dca USE ENTITY WORK.dca (dcaa);
	COMPONENT dcb  -- counter b
		PORT (clk, ce, reset: IN BIT;
		dout: OUT BIT_VECTOR(0 TO sizeb-1));	
		END COMPONENT; 
	  	FOR ALL: dcb USE ENTITY WORK.dcb (dcba);
	COMPONENT dcl -- l (degree of error polynomial in BMA) circuit  
		PORT (clk, ce, reset, bsel: IN BIT; -- dout=1 if l<= cb
		cb: BIT_VECTOR(0 TO sizeb-1); dout: OUT BIT); 
		END COMPONENT; 
	  	FOR ALL: dcL USE ENTITY WORK.dcL (dcLa);
	COMPONENT dci  -- intereleave counter
		PORT (clk, reset: IN BIT; dout: OUT BIT); -- dout=1 if count=0
		END COMPONENT; 
	  	FOR ALL: dci USE ENTITY WORK.dci (dcia);
	SIGNAL cceR, cceS, cceSR, dringCe2, dringPe2: BIT;

	-- VHDL Template
	SIGNAL ca: BIT_VECTOR(0 TO sizea-1); -- counter a
	SIGNAL cb: BIT_VECTOR(0 TO sizeb-1); --  count= ca+ iteration*cb
	SIGNAL res, bsel1, caRes, bufR, bufRa, bufRb, bufS, bufSa, bufSb, bufSR: BIT; 
	SIGNAL chpe1, chpe1a, chpe1b, synpe1,  msmpe1, cei1: BIT;
	-- cei - interleave clock enable
	SIGNAL vdout11, vdout11a, vdout1R, vdout1Ra, vdout1Rb: BIT;
	SIGNAL vdout1S, vdout1Sa, vdout1Sb: BIT;
	SIGNAL ca0, caLast,caNextLast, cb0, cLast, cLasta, cLastb, lCe, lcomp: BIT;
	SIGNAL bufkCeCe, one, vdout11Ce, vdout11In, bufCe1, bufkCe1: BIT;
	SIGNAL noFirstVdoutIn, noFirstVdout, vdout11aDel: BIT;
  BEGIN
	res<= reset OR clast;
	a1: dca
		PORT MAP (clk, res, caLast, ca);
	b1: dcb
		PORT MAP (clk, caLast, res, cb);
	l1: dcl
		PORT MAP (clk, lCe, synpe1, bsel1, cb, lcomp); -- lcomp=1 if cb>=l
	bufkCeCe<= res OR bufR;
	bufk_Ce: drd1ce  -- buffor Clock Enable register
		PORT MAP (clk, bufkCeCe, res, bufkCe1);
	bufkCe<= bufkCe1 AND cei1;

	one<= '1'; 
	vDoutD: drd1ce -- delay vdout by one clock signal: vdout11
		PORT MAP (clk, one, vdout11, vdout);
	vdout11Ce<= reset OR vdout1R OR vdout1S;
	vdout11In<= vdout1S AND NOT reset;
	vdout11P: drd1ce  -- set if vdout1S; reset if reset or vdout1R
		PORT MAP (clk, vdout11Ce, vdout11In, vdout11a);	
	-- After reset the first vdout11a is not valid
	vdout1aDelay: drd1ce
		PORT MAP (clk, one, vdout11a, vdout11aDel); 
	noFirstVdoutIn<= NOT reset AND ((NOT vdout11a AND vdout11aDel) OR noFirstVdout); 
		-- falling edge of vdout1a - set; reset - reset
	noFirstAfterReset: drd1ce
		PORT MAP (clk, one, noFirstVdoutIn, noFirstVdout); 

	vdout11<= vdout11a AND cei1 AND noFirstVdout;

	snce<= ca0;
	chpe<= chpe1;
	synpe<= synpe1;
	synpe1<= ca0 AND cb0;
	vdout1<= vdout11;
	msmpe<= msmpe1;
	bsel<= bsel1;
	bsel1<= drnzero AND (lcomp OR synpe1);

	-- generated by C program
	clastb<= NOT cb(0) AND NOT cb(1) AND cb(2);  -- cb= 4
	clasta<= ca(0) AND NOT ca(1) AND ca(2);  -- ca= 5
	clast<= clasta AND clastb; -- count= 29
	chpe1b<= NOT cb(0) AND cb(1) AND NOT cb(2);  -- cb= 2
	chpe1a<= NOT ca(0) AND NOT ca(1) AND ca(2);  -- ca= 4
	chpe1<= chpe1a AND chpe1b; -- count= 16
	vdout1Rb<= NOT cb(0) AND NOT cb(1) AND cb(2);  -- cb= 4
	vdout1Ra<= NOT ca(0) AND NOT ca(1) AND ca(2);  -- ca= 4
	vdout1R<= vdout1Ra AND vdout1Rb; -- count= 28
	vdout1Sb<= cb(0) AND cb(1) AND NOT cb(2);  -- cb= 3
	vdout1Sa<= NOT ca(0) AND NOT ca(1) AND NOT ca(2);  -- ca= 0
	vdout1S<= vdout1Sa AND vdout1Sb; -- count= 18
	bufRb<= cb(0) AND NOT cb(1) AND NOT cb(2);  -- cb= 1
	bufRa<= ca(0) AND ca(1) AND NOT ca(2);  -- ca= 3
	bufR<= bufRa AND bufRb; -- count= 9
	cb0<= NOT cb(0) AND NOT cb(1) AND NOT cb(2);  -- cb= 0
	lCe<= caLast AND NOT cb0;
	caLast1<= caLast;
	cceR<= ca(0) AND ca(1) AND NOT ca(2);  -- ca= 3
	cceS<= caLast OR synpe1;
	cceSR<= cceS OR cceR;
	cceP: drd1ce
		PORT MAP(clk, cceSR, cceS, cce);
	cbBeg<= cb0;
	c0first<= caNextLast;
	dringPe<= caLast OR  dringPe2;
	dringPe2<= NOT ca(0) AND ca(1) AND NOT ca(2);  -- ca= 2
	msmpe1<= ca(0) AND NOT ca(1) AND NOT ca(2);  -- ca= 1
	ca0<= NOT ca(0) AND NOT ca(1) AND NOT ca(2);  -- ca= 0
	caNextLast<= NOT ca(0) AND NOT ca(1) AND ca(2);  -- ca= 4
	bufSR<= vdout1S OR bufR;
	bufCeP: drd1ce
		PORT MAP (clk, bufSR, vdout1S, bufCe1);
	bufCe<= bufCe1 AND cei1;

	i1: dci
		PORT MAP (clk, reset, cei1);
	cei<= cei1;
END dcounta;	


------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- decoder

	USE WORK.const.ALL;
ENTITY dec IS
PORT (clk, reset, din: IN BIT;
	vdout, dout: OUT BIT);
END dec;

ARCHITECTURE deca OF dec IS

	COMPONENT dbuf   -- input output buffer
		PORT (clk, bufCe, bufkCe, err, vdout1, din: IN BIT;
			dout: OUT BIT);
		END COMPONENT; 
	  	FOR ALL: dbuf USE ENTITY WORK.dbuf (dbufa);
	COMPONENT drd1ce -- single register with clock enable
		PORT ( clk, ce, din: IN BIT; dout: OUT BIT);
		END COMPONENT; 
	  	FOR ALL: drd1ce USE ENTITY WORK.drd1ce (drd1cea);
	COMPONENT dmul21 
		PORT ( sel: IN BIT; d0, d1: IN BIT_VECTOR(0 TO m-1); 
			dout: OUT BIT_VECTOR(0 TO m-1));  
		END COMPONENT; 
	  	FOR ALL: dmul21 USE ENTITY WORK.dmul21 (dmul21a);
	COMPONENT drd     -- PIPO register
	  	PORT (clk: IN BIT; din: IN BIT_VECTOR(0 TO m-1); 
			dout: OUT BIT_VECTOR(0 TO m-1));  
		END COMPONENT;
	  	FOR ALL: drd USE ENTITY WORK.drd (drda);
	COMPONENT drdce   -- PIPO register
	  	PORT (clk, ce: IN BIT; din: IN BIT_VECTOR(0 TO m-1); 
			dout: OUT BIT_VECTOR(0 TO m-1));  
		END COMPONENT;
	  	FOR ALL: drdce USE ENTITY WORK.drdce (drdcea);
	COMPONENT drdcer   -- PIPO register
	  	PORT (clk, ce, reset: IN BIT; din: IN BIT_VECTOR(0 TO m-1); 
			dout: OUT BIT_VECTOR(0 TO m-1));  
		END COMPONENT;
	  	FOR ALL: drdcer USE ENTITY WORK.drdcer (drdcera);
	COMPONENT drdcesone   -- m registers with CE and if set='1' dout<=din0&"00.." 
		PORT ( clk, ce, set, dinone: IN BIT; din: IN BIT_VECTOR(0 TO m-1); 
			dout: OUT BIT_VECTOR(0 TO m-1));
		END COMPONENT;
	  	FOR ALL: drdcesone USE ENTITY WORK.drdcesone (drdcesonea);
	COMPONENT dpm    -- Parallel dual basis multiplier
		PORT (din1, din2: IN BIT_VECTOR(0 TO m-1); 
			dout: OUT BIT_VECTOR(0 TO m-1));  
		END COMPONENT;
	  	FOR ALL: dpm USE ENTITY WORK.dpm (dpma);
	COMPONENT dxorm            -- dout<= din1 xor din0; opt.1
		PORT (din0, din1: IN BIT_VECTOR(0 TO m-1);
			dout: OUT BIT_VECTOR(0 TO m-1));
		END COMPONENT;
	  	FOR ALL: dxorm USE ENTITY WORK.dxorm (dxorma);


		-- OPTION 3
	COMPONENT dshr   -- shift register with reset and serial XOR, opt.3
		PORT (clk, ce, reset, din: IN BIT;
			dout: OUT BIT_VECTOR(0 TO m-1)); 
		END COMPONENT;
	  	FOR ALL: dshr USE ENTITY WORK.dshr (dshra);
	COMPONENT dshpe   -- shift register with parallel in and serial XOR, opt.3
		PORT (clk, ce, pe: IN BIT; din: IN BIT_VECTOR(0 TO m-1);
			dout: OUT BIT_VECTOR(0 TO m-1)); 
		END COMPONENT;
	  	FOR ALL: dshpe USE ENTITY WORK.dshpe (dshpea);
	COMPONENT dsdbm -- serial dual basis maltiplier wirhout ring, opt.3
		PORT (dbin, sbin: IN BIT_VECTOR(0 TO m-1); dout: OUT BIT);
		END COMPONENT;
	  	FOR ALL: dsdbm USE ENTITY WORK.dsdbm (dsdbma);
	COMPONENT  dsdbmRing  -- serial dual basis maltiplier ring, opt.3
		PORT (clk, pe: IN BIT;   -- pe- parellel enable
			din: IN BIT_VECTOR(0 TO m-1);
			dout: OUT BIT_VECTOR(0 TO m-1)); 
		END COMPONENT;
	  	FOR ALL: dsdbmRing USE ENTITY WORK.dsdbmRing (dsdbmRinga);
	COMPONENT dssbm   -- serial standard basis multiplier ring, opt3
		PORT (clk, ce, pe: IN BIT; din: IN BIT_VECTOR(0 TO m-1); 
			dout: OUT BIT_VECTOR(0 TO m-1)); 
		END COMPONENT;
	  	FOR ALL: dssbm USE ENTITY WORK.dssbm (dssbma);
	COMPONENT dmli  -- multiply by alpha^i (1 + x^i + x^m; for m!=8), opt.3
		PORT (din: IN BIT_VECTOR(0 TO m-1);
 			dout: OUT BIT_VECTOR(0 TO m-1));
		END COMPONENT;
	  	FOR ALL: dmli USE ENTITY WORK.dmli (dmlia);
	COMPONENT dinv  -- inverter
		PORT (clk, cbBeg, bsel, caLast, cce, drnzero, snce, synpe: IN BIT;  -- pe- parallel enable - if dr!=0; 
			din: IN BIT_VECTOR(0 TO m-1);
			dout: OUT BIT_VECTOR(0 TO m-1));
		END COMPONENT;
	  	FOR ALL: dinv USE ENTITY WORK.dinv (dinva);
	COMPONENT dandm  -- dout<= din AND en
		PORT (en: IN BIT; din: IN BIT_VECTOR(0 TO m-1);
		dout: OUT BIT_VECTOR(0 TO m-1));
		END COMPONENT;
	  	FOR ALL: dandm USE ENTITY WORK.dandm (dandma);
	
		-- common
	COMPONENT dxort                       -- (t-1) * XOR
		PORT (din0, din1, din2, din3: IN BIT; dout: OUT BIT);
		END COMPONENT;
	  	FOR ALL: dxort USE ENTITY WORK.dxort (dxorta);
	COMPONENT dcheq   -- check if Chien search circuit is zero
		PORT (din1, din2, din3: IN BIT_VECTOR(0 TO m-1); 
			dout: OUT BIT); -- dout=1 if an error occur
		END COMPONENT;
	  	FOR ALL: dcheq USE ENTITY WORK.dcheq (dcheqa);

	-- SYNDROMS & CHIEN SEARCH
	COMPONENT dsyn1
		PORT (clk, ce, pe, din: IN BIT;
		dout1, dout2, dout4: OUT BIT_VECTOR(0 TO m-1));
		END COMPONENT;
 		FOR ALL: dsyn1 USE ENTITY WORK.dsyn1 (dsyn1a);
	COMPONENT dsyn3
		PORT (clk, ce, pe, din: IN BIT;
		dout3: OUT BIT_VECTOR(0 TO m-1));
		END COMPONENT;
 		FOR ALL: dsyn3 USE ENTITY WORK.dsyn3 (dsyn3a);
	COMPONENT dsyn5
		PORT (clk, ce, pe, din: IN BIT;
		dout5: OUT BIT_VECTOR(0 TO m-1));
		END COMPONENT;
 		FOR ALL: dsyn5 USE ENTITY WORK.dsyn5 (dsyn5a);
	COMPONENT dch1
		PORT (clk, ce, pe: IN BIT; din: IN BIT_VECTOR(0 TO m-1);
			dout: OUT BIT_VECTOR(0 TO m-1));
		END COMPONENT;
		FOR ALL: dch1 USE ENTITY WORK.dch1 (dch1a);
	COMPONENT dch2
		PORT (clk, ce, pe: IN BIT; din: IN BIT_VECTOR(0 TO m-1);
			dout: OUT BIT_VECTOR(0 TO m-1));
		END COMPONENT;
		FOR ALL: dch2 USE ENTITY WORK.dch2 (dch2a);
	COMPONENT dch3
		PORT (clk, ce, pe: IN BIT; din: IN BIT_VECTOR(0 TO m-1);
			dout: OUT BIT_VECTOR(0 TO m-1));
		END COMPONENT;
		FOR ALL: dch3 USE ENTITY WORK.dch3 (dch3a);

	-- common signals generated by C program
	SIGNAL syn1, syn2, syn3, syn4, syn5: BIT_VECTOR(0 TO m-1);
	SIGNAL sn0out, sn1out, sn2out, sn3out, sn4out: BIT_VECTOR(0 TO m-1);
	SIGNAL sn0in, sn1in, sn2in, sn3in: BIT_VECTOR(0 TO m-1);
	SIGNAL c1out, c2out, c3out: BIT_VECTOR(0 TO m-1);
	SIGNAL b3out: BIT_VECTOR(0 TO m-1);
	SIGNAL ch1out, ch2out, ch3out: BIT_VECTOR(0 TO m-1);

	-- for different option by C program
	SIGNAL cei: BIT; -- interleve CE
	SIGNAL sn0en, sn1en, sn2en, sn3en: BIT_VECTOR(0 TO m-1);
	COMPONENT dcount --counter
		PORT (clk, reset, drnzero: IN BIT;
		bsel, bufCe, bufkCe, chpe, msmpe, snce, synpe, vdout, vdout1, c0first, cce, caLast1, cbBeg, dringPe, cei: OUT BIT);
		END COMPONENT;
		FOR ALL: dcount USE ENTITY WORK.dcount (dcounta);

	--  option 3 VHDL template
	SIGNAL  chpe, msmPe, msmCe, snce, synpe, vdout1, caLast: BIT; 
	SIGNAL  cce, cbBeg: BIT; 
		-- from counter - control signals
	SIGNAL err, bsel, bufCe, bufkCe: BIT;
	SIGNAL b3set, b3sIn, b2out, b2ce, b3ce, xbsel: BIT;  
		-- bsel=1 - Br+1<- Br*x^2 
	SIGNAL drnzero, dringPe, ccCe, qdr_or, qdr_orCe: BIT;
	SIGNAL one, c0first: BIT;
	SIGNAL c1in, cs, dr, dra, dr_or: BIT_VECTOR(0 TO m-1);
	SIGNAL drpd, qd, dli, dmIn, dm: BIT_VECTOR(0 TO m-1);
	SIGNAL cin: BIT_VECTOR(2 TO t);
  BEGIN
	b2: drd1ce
		PORT MAP (clk, b2ce, bsel, b2out);
	b3ce<= caLast AND NOT cbBeg;
	b2ce<= synpe OR b3ce;

	dr_or(0)<= dra(0);  -- dr_or<= dra(0) OR dra(1) ... OR dra(m-1)
	gen_dr:
	FOR i IN 1 TO m-1 GENERATE
		dr_or(i)<= dr_or(i-1) OR dra(i);
	END GENERATE;
	qdr_orCe<= synpe OR caLast;
	qdrOr: drd1ce
		PORT MAP (clk, qdr_orCe, dr_or(m-1), qdr_or);
	drnzero<= (synpe AND dr_or(m-1)) OR (NOT synpe AND qdr_or);
	msmCe<= NOT caLast;
	msm: dssbm
		PORT MAP (clk, msmce, msmpe, cs, dr);	

	xdr: dmul21
		PORT MAP (synpe, dr, syn1, dra);
	
	inv: dinv
		PORT MAP (clk, cbBeg, bsel, caLast, cce, drnzero, snce, synpe, dra, drpd);
		-- c0first - count next to the last
	qdd: drdce
		PORT MAP (clk, caLast, drpd, qd);

	b3set<= synpe OR (b3ce AND NOT bsel);
	b3sIn<= synpe AND NOT drnzero;
	b3:  drdcesone
		PORT MAP (clk, b3ce, b3set, b3sIn, c1out, b3out);
	xbsel<= bsel OR cbBeg;  -- cbBeg to reset b:
	ccCe<= (msmPe AND cbBeg) OR caLast;
	c1in<= syn1(m-1) & syn1(0 TO m-2);
	c1: dshpe
		PORT MAP (clk, cce, synpe, c1in, c1out);
	cin(2)<= dm(0) AND b2out AND NOT cbBeg;
	-- for m!= 8
	mli: dmli  -- multiply by second nonzero coeffiecient no
		PORT MAP (drpd, dli);
	xdm: dmul21
		PORT MAP (caLast, qd, dli, dmIn);
	dring: dsdbmRing
		PORT MAP (clk, dringPe, dmIn, dm);	

	--------- for option 3 C program 
	sn0e: dandm
		PORT MAP (c0first, sn0out, sn0en);
	sn1e: dandm
		PORT MAP (c1out(0), sn1out, sn1en);
	sn2e: dandm
		PORT MAP (c2out(0), sn2out, sn2en);
	sn3e: dandm
		PORT MAP (c3out(0), sn3out, sn3en);
	ms0: dxort
		PORT MAP (sn0en(0), sn1en(0), sn2en(0), sn3en(0), cs(0));
	ms1: dxort
		PORT MAP (sn0en(1), sn1en(1), sn2en(1), sn3en(1), cs(1));
	ms2: dxort
		PORT MAP (sn0en(2), sn1en(2), sn2en(2), sn3en(2), cs(2));
	ms3: dxort
		PORT MAP (sn0en(3), sn1en(3), sn2en(3), sn3en(3), cs(3));
	c2: dshr
		PORT MAP (clk, cce, cbBeg, cin(2), c2out);
	c3: dshr
		PORT MAP (clk, cce, cbBeg, cin(3), c3out);
	mb3: dsdbm
		PORT MAP (b3out, dm, cin(3));
	count: dcount
		PORT MAP (clk, reset, drnzero, bsel, bufCe, bufkCe, chpe, msmPe, snce, synpe, vdout, vdout1, c0first, cce, caLast, cbBeg, dringPe, cei);


	--------- common C program
	s1: dsyn1
		PORT MAP (clk, cei, synpe, din,  syn1, syn2, syn4);
	s3: dsyn3
		PORT MAP (clk, cei, synpe, din,  syn3);
	s5: dsyn5
		PORT MAP (clk, cei, synpe, din,  syn5);
	x0: dmul21
		PORT MAP (synpe, sn3out, syn3, sn0in);
	x1: dmul21
		PORT MAP (synpe, sn4out, syn2, sn1in);
	x2: dmul21
		PORT MAP (synpe, sn0out, syn1, sn2in);
	x3: dmul21
		PORT MAP (synpe, sn1out, syn5, sn3in);
	sn0: drdce
		PORT MAP (clk, snce, sn0in, sn0out);
	sn1: drdce
		PORT MAP (clk, snce, sn1in, sn1out);
	sn2: drdce
		PORT MAP (clk, snce, sn2in, sn2out);
	sn3: drdce
		PORT MAP (clk, snce, sn3in, sn3out);
	sn4: drdce
		PORT MAP (clk, synpe, syn4, sn4out);
	ch1: dch1
		PORT MAP (clk, cei, chpe, c1out, ch1out);
	ch2: dch2
		PORT MAP (clk, cei, chpe, c2out, ch2out);
	ch3: dch3
		PORT MAP (clk, cei, chpe, c3out, ch3out);
	cheg: dcheq
		PORT MAP (ch1out, ch2out, ch3out,  err);

	--- common for all option VHDL template 
	one<= '1';
	buf: dbuf
		PORT MAP (clk, bufCe, bufkCe, err, vdout1, din, dout);
END deca;