dec.vhd

it is used to understand the basic working of a BCH encoder/Decoder

END dxorta;


--------------------------------------------------------------------

-- Multiply by L^i, where gen. polynomial= 1+ x^i + x^m (for m!=8)

	USE WORK.const.ALL;
ENTITY dmli IS
PORT (din: IN BIT_VECTOR(0 TO m-1);
 	dout: OUT BIT_VECTOR(0 TO m-1));
END dmli;

ARCHITECTURE dmlia OF dmli IS
BEGIN
	dout(0)<= din(1);
	dout(1)<= din(2);
	dout(2)<= din(3);
	dout(3)<= din(0) XOR din(1);
END dmlia;

---------------------------------------------------------------------------
-- squaring dout<= (din)^2 in standard basis -- for inverse calculator

	USE WORK.const.ALL;
ENTITY dsq IS
PORT ( din: IN BIT_VECTOR(0 TO m-1); 
	dout: OUT BIT_VECTOR(0 TO m-1)); -- serial output 
END dsq;

ARCHITECTURE dsqa OF dsq IS
	SIGNAL dxor: BIT_VECTOR(0 TO 3);
  BEGIN
	dxor(0 TO m-1)<= din;
		-- optimalization saving = 0 XOR gates
	dout(0)<= dxor(0) XOR dxor(2);
	dout(1)<= dxor(2);
	dout(2)<= dxor(1) XOR dxor(3);
	dout(3)<= dxor(3);
	-- no. XOR gates = 2
 
END dsqa;

-----------------------------------------------------------------------------
-- m* registers with reset to dual basis one

	USE WORK.const.ALL;
ENTITY drdrDualOne IS
PORT (clk, ce, reset: BIT;
	din: IN BIT_VECTOR(0 TO m-1); 
	dout: OUT BIT_VECTOR(0 TO m-1)); -- serial output 
END drdrDualOne;

ARCHITECTURE drdrDualOnea OF drdrDualOne IS
	SIGNAL q: BIT_VECTOR(0 TO m-1);
  BEGIN
	dout<= q;
  PROCESS BEGIN
	WAIT UNTIL clk'EVENT AND clk='1';
	IF reset='1' THEN
		q<= "1000";
	ELSIF ce='1' THEN
		q<= din;
	ELSE 
		q<= q;
	END IF;
  END PROCESS;
END drdrDualOnea;

----------------------------------------------------------------------------------
-- Inventer dout<= din^(-1)<= din^(2)*din^(4)*...*din^(2^(m-1))

	USE WORK.const.ALL;
ENTITY dinv IS
PORT (clk, cbBeg, bsel, caLast, cce, drnzero, snce, synpe: IN BIT;  
	din: IN BIT_VECTOR(0 TO m-1); --input data selected by sel_in
	dout: OUT BIT_VECTOR(0 TO m-1));
END dinv;

ARCHITECTURE dinva OF dinv IS
	SIGNAL qsq, sq, msin, mdin, mout: BIT_VECTOR(0 TO m-1);
	-- sq- square, q??- RD out, m??? - parallel multiplier, ?d/s -dual standard basis
	SIGNAL ce1, ce2a, ce2b, ce2, reset, sel: BIT;
	
	COMPONENT dmul21   -- 2-1 multiplexer
	  	PORT ( sel: IN BIT; d0, d1: IN BIT_VECTOR(0 TO m-1); 
			dout: OUT BIT_VECTOR(0 TO m-1)); 
		END COMPONENT;
	  	FOR ALL: dmul21 USE ENTITY WORK.dmul21 (dmul21a);
	COMPONENT drdce     -- PIPO register
	  	PORT (clk, ce: IN BIT; din: IN BIT_VECTOR(0 TO m-1); 
			dout: OUT BIT_VECTOR(0 TO m-1));  
		END COMPONENT;
	  	FOR ALL: drdce USE ENTITY WORK.drdce (drdcea);
	COMPONENT drdrDualOne -- registers with and reset to dual basis one
		PORT (clk, ce, reset: IN BIT; din: IN BIT_VECTOR(0 TO m-1); 
			dout: OUT BIT_VECTOR(0 TO m-1)); 
		END COMPONENT;
	  	FOR ALL: drdrDualOne USE ENTITY WORK.drdrDualOne (drdrDualOnea);
	COMPONENT dsq    -- dout<= (din)^2
	  	PORT ( din: IN BIT_VECTOR(0 TO m-1);
			dout: OUT BIT_VECTOR(0 TO m-1));
		END COMPONENT;
		FOR ALL: dsq USE ENTITY WORK.dsq (dsqa);
	COMPONENT dpdbm    -- Parallel dual basis multiplier
		PORT (ddin, dsin: IN BIT_VECTOR(0 TO m-1); 
			dout: OUT BIT_VECTOR(0 TO m-1));  
		END COMPONENT;
	  	FOR ALL: dpdbm USE ENTITY WORK.dpdbm (dpdbma);
  BEGIN
	ce1<= ce2 OR caLast OR synpe;
	ce2a<= drnzero AND cbBeg;
	ce2b<= bsel OR ce2a;
	ce2<= cce AND NOT snce AND ce2b;
	reset<= (snce AND bsel) OR synpe;
	sel<= caLast OR synpe;

	dout<= mout;
	x1: dmul21
	  PORT MAP (sel, qsq, din, msin);
	s1: dsq
	  PORT MAP (msin, sq);
	q1: drdce  
	  PORT MAP (clk, ce1, sq, qsq);
	q2: drdrDualOne
	  PORT MAP (clk, ce2, reset, mout, mdin);
	m1: dpdbm
	  PORT MAP (mdin, msin, mout);
END dinva;

---------------------------------------------------------------------------------
-- Find if chien search circuit is equil 0

	USE WORK.const.ALL;
ENTITY dcheq IS
PORT (din1, din2, din3: IN BIT_VECTOR(0 TO m-1); 
	dout: OUT BIT); -- dout=1 if equil 
END dcheq;

ARCHITECTURE dcheqa OF dcheq IS
	SIGNAL eq: BIT_VECTOR(0 TO m-1);
  BEGIN
	eq(0)<= NOT din1(0) XOR din2(0) XOR din3(0);
	eq(1)<= din1(1) XOR din2(1) XOR din3(1);
	eq(2)<= din1(2) XOR din2(2) XOR din3(2);
	eq(3)<= din1(3) XOR din2(3) XOR din3(3);
	dout<= NOT (eq(0) OR eq(1) OR eq(2) OR eq(3));
END dcheqa;

----------------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Syndroms calculation circuits

	USE WORK.const.ALL;
ENTITY dsyn1 IS
PORT (clk, ce, pe ,din: IN BIT;
	dout1, dout2, dout4: OUT BIT_VECTOR(0 TO m-1));
END dsyn1;

ARCHITECTURE dsyn1a OF dsyn1 IS
	SIGNAL syn: BIT_VECTOR(0 TO 5);
  BEGIN
	syn(4)<= syn(1) XOR syn(3); -- 2
	syn(5)<= syn(0) XOR syn(2); -- 1
		-- Saving due to optimisation = 3
	dout1(0 TO m-1)<= syn(0 TO m-1);
	dout2(0)<= syn(5);
	dout2(1)<= syn(2);
	dout2(2)<= syn(4);
	dout2(3)<= syn(3);
	dout4(0)<= syn(4) XOR syn(5);
	dout4(1)<= syn(4);
	dout4(2)<= syn(2) XOR syn(3);
	dout4(3)<= syn(3);
  PROCESS BEGIN
	WAIT UNTIL clk'EVENT AND clk='1';
	IF pe='1' THEN
	  syn(0)<= din;
	  syn(1 TO 3)<= "000";
	ELSIF ce='1' THEN
	  syn(0)<= syn(3) XOR din;
	  syn(1)<= syn(0) XOR syn(3);
	  syn(2)<= syn(1);
	  syn(3)<= syn(2);
	END IF;
  END PROCESS;
END dsyn1a;


	USE WORK.const.ALL;
ENTITY dsyn3 IS
PORT (clk, ce, pe ,din: IN BIT;
	dout3: OUT BIT_VECTOR(0 TO m-1));
END dsyn3;

ARCHITECTURE dsyn3a OF dsyn3 IS
	SIGNAL syn: BIT_VECTOR(0 TO 3);
  BEGIN
	dout3<= syn;
  PROCESS BEGIN
	WAIT UNTIL clk'EVENT AND clk='1';
	IF pe='1' THEN
	  syn(0)<= din;
	  syn(1 TO 3)<= "000";
	ELSIF ce='1' THEN
	syn(0)<= din XOR syn(1);
	syn(1)<= syn(1) XOR syn(2);
	syn(2)<= syn(2) XOR syn(3);
	syn(3)<= syn(0) XOR syn(3);
	END IF;
  END PROCESS;
END dsyn3a;


	USE WORK.const.ALL;
ENTITY dsyn5 IS
PORT (clk, ce, pe ,din: IN BIT;
	dout5: OUT BIT_VECTOR(0 TO m-1));
END dsyn5;

ARCHITECTURE dsyn5a OF dsyn5 IS
	SIGNAL syn: BIT_VECTOR(0 TO 1);
  BEGIN
		-- Saving due to optimisation = 0
	dout5(0)<= syn(0);
	dout5(1)<= syn(1);
	dout5(2)<= syn(1);
	dout5(3)<= '0';
  PROCESS BEGIN
	WAIT UNTIL clk'EVENT AND clk='1';
	IF pe='1' THEN
	  syn(0)<= din;
	  syn(1 TO 1)<= "0";
	ELSIF ce='1' THEN
	  syn(0)<= syn(1) XOR din;
	  syn(1)<= syn(0) XOR syn(1);
	END IF;
  END PROCESS;
END dsyn5a;


---------------------------------------------------------------------------
-- Chien search circuits

	USE WORK.const.ALL;
ENTITY dch1 IS
PORT (clk, ce, pe: IN BIT;
	din: IN BIT_VECTOR(0 TO m-1);
	dout: OUT BIT_VECTOR(0 TO m-1));
END dch1;

ARCHITECTURE dch1a OF dch1 IS
	SIGNAL chin: BIT_VECTOR(0 TO m-1); -- registers input
	SIGNAL ch: BIT_VECTOR(0 TO 3); -- ch registers and optimisation
  BEGIN
	dout<= ch(0 TO m-1);
	chin(0)<= ch(3);
	chin(1)<= ch(0) XOR ch(3);
	chin(2)<= ch(1);
	chin(3)<= ch(2);
  PROCESS BEGIN
	WAIT UNTIL clk'EVENT AND clk='1';
	IF pe='1' THEN
	  ch(0 TO m-1)<= din;
	ELSIF ce='1' THEN
	  ch(0 TO m-1)<= chin;
	END IF;
  END PROCESS;
	-- number XOR gates= 1;
END dch1a;


	USE WORK.const.ALL;
ENTITY dch2 IS
PORT (clk, ce, pe: IN BIT;
	din: IN BIT_VECTOR(0 TO m-1);
	dout: OUT BIT_VECTOR(0 TO m-1));
END dch2;

ARCHITECTURE dch2a OF dch2 IS
	SIGNAL chin: BIT_VECTOR(0 TO m-1); -- registers input
	SIGNAL ch: BIT_VECTOR(0 TO 3); -- ch registers and optimisation
  BEGIN
	dout<= ch(0 TO m-1);
	chin(0)<= ch(2);
	chin(1)<= ch(2) XOR ch(3);
	chin(2)<= ch(0) XOR ch(3);
	chin(3)<= ch(1);
  PROCESS BEGIN
	WAIT UNTIL clk'EVENT AND clk='1';
	IF pe='1' THEN
	  ch(0 TO m-1)<= din;
	ELSIF ce='1' THEN
	  ch(0 TO m-1)<= chin;
	END IF;
  END PROCESS;
	-- number XOR gates= 2;
END dch2a;


	USE WORK.const.ALL;
ENTITY dch3 IS
PORT (clk, ce, pe: IN BIT;
	din: IN BIT_VECTOR(0 TO m-1);
	dout: OUT BIT_VECTOR(0 TO m-1));
END dch3;

ARCHITECTURE dch3a OF dch3 IS
	SIGNAL chin: BIT_VECTOR(0 TO m-1); -- registers input
	SIGNAL ch: BIT_VECTOR(0 TO 3); -- ch registers and optimisation
  BEGIN
	dout<= ch(0 TO m-1);
	chin(0)<= ch(1);
	chin(1)<= ch(1) XOR ch(2);
	chin(2)<= ch(2) XOR ch(3);
	chin(3)<= ch(0) XOR ch(3);
  PROCESS BEGIN
	WAIT UNTIL clk'EVENT AND clk='1';
	IF pe='1' THEN
	  ch(0 TO m-1)<= din;
	ELSIF ce='1' THEN
	  ch(0 TO m-1)<= chin;
	END IF;
  END PROCESS;
	-- number XOR gates= 3;
END dch3a;


-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- CONTROL ENTITIES - counters
-- counter a

	USE WORK.const.ALL;
ENTITY dca IS
PORT (clk, reset: IN BIT;
	cRes: OUT BIT; -- cRes<= countLast OR  reset
	dout: OUT BIT_VECTOR(0 TO sizea-1)); -- count
END dca;

ARCHITECTURE dcaa OF dca IS
	SIGNAL ca, cin, cand: BIT_VECTOR(0 TO sizea-1);
	SIGNAL CRes1, cLast: BIT;
  BEGIN
	dout<= ca;
	cRes<= cRes1;
	cRes1<= cLast OR reset;
	cLast<= ca(0) AND NOT ca(1) AND ca(2);  -- ca= 5
		--cLast=1 - when c= iteration-1
	cand(0)<= ca(0);
	cin(0)<= NOT ca(0);

	   gen_cin:
	FOR i IN 1 TO sizea-1 GENERATE
		cin(i)<= cand(i-1) XOR ca(i);
	END GENERATE;
	  den_cand_if:
	IF sizea>2 GENERATE
	  gen_cand:
	  FOR i IN 1 TO sizea-2 GENERATE
		cand(i)<= ca(i) AND cand(i-1);
	  END GENERATE;
	END GENERATE;
  PROCESS BEGIN
	WAIT UNTIL clk'EVENT AND clk='1';
	FOR i IN 0 TO sizea-1 LOOP
	  IF cRes1='1' THEN
        	ca(i)<= '0';	
	  ELSE
		ca(i)<= cin(i);
	  END IF;
	END LOOP;
  END PROCESS;
END dcaa;

-------------------------------------------------------------------------------
-- interleave counter - copied only if interleave>1

	USE WORK.const.ALL;
ENTITY dci IS
PORT (clk, reset: IN BIT;
	dout: OUT BIT); -- dout=1 if count=0
END dci;

ARCHITECTURE dcia OF dci IS
	CONSTANT sizei: INTEGER:= 1; -- =log2(interleave)
	SIGNAL ci, cin, cand: BIT_VECTOR(0 TO sizei-1);
	SIGNAL cBeg, cLast, res: BIT;
  BEGIN
	dout<= cBeg;
	res<= cLast OR reset;
	--cLast=1 - when ci= interleave-1
	cLast<= ci(0);  -- ci= 1
	cBeg<= NOT ci(0);  -- ci= 0
	cand(0)<= ci(0);
	cin(0)<= NOT ci(0);

  PROCESS BEGIN
	WAIT UNTIL clk'EVENT AND clk='1';
	FOR i IN 0 TO sizei-1 LOOP
	  IF res='1' THEN
        	ci(i)<= '0';	
	  ELSE
		ci(i)<= cin(i);
	  END IF;
	END LOOP;
  END PROCESS;
END dcia;

-------------------------------------------------------------------------------
-- counter b -- no. of cicles count= iteration*cb +ca 

	USE WORK.const.ALL;
ENTITY dcb IS
PORT (clk, ce, reset: IN BIT;
	dout: OUT BIT_VECTOR(0 TO sizeb-1)); -- count
END dcb;

ARCHITECTURE dcba OF dcb IS
	SIGNAL cb, cin, cand: BIT_VECTOR(0 TO sizeb-1);
  BEGIN
	dout<= cb;
	cand(0)<= cb(0);
	cin(0)<= NOT cb(0);

	   gen_cin:
	FOR i IN 1 TO sizeb-1 GENERATE
		cin(i)<= cand(i-1) XOR cb(i);
	END GENERATE;
		gen_cand:
	FOR i IN 1 TO sizeb-2 GENERATE
		cand(i)<= cb(i) AND cand(i-1);
	END GENERATE;
  PROCESS BEGIN
	WAIT UNTIL clk'EVENT AND clk='1';
	FOR i IN 0 TO sizeb-1 LOOP
	  IF reset='1' THEN
        	cb(i)<= '0';	
	  ELSIF ce='1' THEN
		cb(i)<= cin(i);
	  END IF;
	END LOOP;
  END PROCESS;
END dcba;
-------------------------------------------------------------------------------
-- l (degree of error polynomial in BMA) circuit  

	USE WORK.const.ALL;
ENTITY dcl IS
PORT (clk, ce, reset, bsel: IN BIT;
	cb: BIT_VECTOR(0 TO sizeb-1);
	dout: OUT BIT); -- dout=1 if l<= cb
END dcl;

ARCHITECTURE dcla OF dcl IS