dec.vhd

it is used to understand the basic working of a BCH encoder/Decoder

-- File generated by bch.exe program.
-- The decoder for BCH code (15,5), t=3
-- Option= 3,  Interleave= 2, -- with optimisation.
-- GF(2^4) is generated by polynomial [1+x+...] - 11001;
 
-- COMMON option drd invCe dinv DualOne dpdbm dcount
-------------------------------------------------------------------
-- 2-1 multiplexer

	USE WORK.const.ALL;
ENTITY dmul21 IS
PORT ( sel: IN BIT;
	d0, d1: IN BIT_VECTOR(0 TO m-1); 
	dout: OUT BIT_VECTOR(0 TO m-1));  
END dmul21;

ARCHITECTURE dmul21a OF dmul21 IS
  BEGIN
	gen:
	FOR i IN 0 TO m-1 GENERATE
	  dout(i)<= (NOT sel AND d0(i)) OR (sel AND d1(i));
	END GENERATE;
END dmul21a;

--------------------------------------------------------------------
-- single register with clock enable

ENTITY drd1ce IS
PORT ( clk, ce, din: IN BIT; 
	dout: OUT BIT);  
END drd1ce;

ARCHITECTURE drd1cea OF drd1ce IS
	SIGNAL q: BIT;
  BEGIN
	dout<= q;
  PROCESS BEGIN
	WAIT UNTIL clk'EVENT AND clk='1';
	IF ce='1' THEN
		q<= din;
	ELSE
		q<= q;
	END IF;
  END PROCESS;
END drd1cea;

--------------------------------------------------------------------
-- PIPO registers m bits wide with clock enable and reset

	USE WORK.const.ALL;
ENTITY drdcer IS
PORT ( clk, ce, reset: IN BIT;
	din: IN BIT_VECTOR(0 TO m-1); 
	dout: OUT BIT_VECTOR(0 TO m-1));  
END drdcer;

ARCHITECTURE drdcera OF drdcer IS
	SIGNAL q: BIT_VECTOR(0 TO m-1);
  BEGIN
	dout<= q;
  PROCESS BEGIN
	WAIT UNTIL clk'EVENT AND clk='1';
	FOR i IN 0 TO m-1 LOOP
	  IF reset='1' THEN
		q(i)<= '0';
	  ELSIF ce='1' THEN
		q(i)<= din(i);
          ELSE 
		q(i)<= q(i);
	  END IF;
	END LOOP;
  END PROCESS;
END drdcera;

--------------------------------------------------------------------
-- PIPO registers m bits wide with clock enable and set to one

	USE WORK.const.ALL;
ENTITY drdceSOne IS
PORT ( clk, ce, set, dinone: IN BIT;
	din: IN BIT_VECTOR(0 TO m-1); 
	dout: OUT BIT_VECTOR(0 TO m-1));  
END drdcesone;

ARCHITECTURE drdcesonea OF drdcesone IS
	SIGNAL q: BIT_VECTOR(0 TO m-1);
  BEGIN
	dout<= q;
  PROCESS BEGIN
	WAIT UNTIL clk'EVENT AND clk='1';
	IF set='1' THEN 
		q(0)<= dinone;
	ELSIF ce='1' THEN
		q(0)<= din(0);
	ELSE
		q(0)<= q(0);
	END IF;
	
	FOR i IN 1 TO m-1 LOOP
	  IF set='1' THEN
		q(i)<= '0';
	  ELSIF ce='1' THEN
		q(i)<= din(i);
	  ELSE
		q(i)<= q(i);
          END IF;
	END LOOP;
  END PROCESS;
END drdcesonea;


--------------------------------------------------------------------
-- m registers with clock enable

	USE WORK.const.ALL;
ENTITY drdce IS
PORT ( clk, ce: IN BIT;
	din: IN BIT_VECTOR(0 TO m-1); 
	dout: OUT BIT_VECTOR(0 TO m-1));  
END drdce;

ARCHITECTURE drdcea OF drdce IS
	SIGNAL q: BIT_VECTOR(0 TO m-1);
  BEGIN
	dout<= q;
  PROCESS BEGIN
	WAIT UNTIL clk'EVENT AND clk='1';
	IF ce='1' THEN
		q<= din;
	ELSE
		q<= q;
	END IF;
  END PROCESS;
END drdcea;
--------------------------------------------------------------------
-- PIPO registers m bits wide

	USE WORK.const.ALL;
ENTITY drd IS
PORT (clk: IN BIT;
	din: IN BIT_VECTOR(0 TO m-1); 
	dout: OUT BIT_VECTOR(0 TO m-1));  
END drd;

ARCHITECTURE drda OF drd IS
	SIGNAL q: BIT_VECTOR(0 TO m-1);
  BEGIN
	dout<= q;
  PROCESS BEGIN
	WAIT UNTIL clk'EVENT AND clk='1';
	q<= din;
  END PROCESS;
END drda;

-- sumator m * XOR; dout<= din0 XOR din1

	USE WORK.const.ALL;
ENTITY dxorm IS
PORT (din0, din1: IN BIT_VECTOR(0 TO m-1);
	dout: OUT BIT_VECTOR(0 TO m-1));
END dxorm;

ARCHITECTURE dxorma OF dxorm IS
  BEGIN
	dout<= din0 XOR din1;
END dxorma;

-----------------------------------------------------------------

--------------- OPTION 3 -serial
-------------------------------------------------------------------
-- Serial In Parallel Out m bits shift register

	USE WORK.const.ALL;
ENTITY dsipo IS
PORT (clk, din: IN BIT;
	dout: OUT BIT_VECTOR(0 TO m-1)); 
END dsipo;

ARCHITECTURE dsipoa OF dsipo IS
	SIGNAL q: BIT_VECTOR(0 TO m-1);
  BEGIN
	dout<= q;
  PROCESS BEGIN
	WAIT UNTIL clk'EVENT AND clk='1';
	q<= din & q(0 TO m-2);
  END PROCESS;
END dsipoa;

-------------------------------------------------------------------
-- Shift refister with serilial XOR, and parallel in

	USE WORK.const.ALL;
ENTITY dshpe IS
PORT (clk, ce, pe: IN BIT;
	din: IN BIT_VECTOR(0 TO m-1); -- parallel in
	dout: OUT BIT_VECTOR(0 TO m-1)); 
END dshpe;

ARCHITECTURE dshpea OF dshpe IS
	SIGNAL ring: BIT_VECTOR(0 TO m-1);
  BEGIN
	dout<= ring;
  PROCESS BEGIN
	WAIT UNTIL clk'EVENT AND clk='1';
	IF pe= '1' THEN
	  ring<= din;	
	ELSIF ce='1' THEN
	  ring<= ring(m-1) & ring(0 TO m-2);
	END IF;
  END PROCESS;
END dshpea;

-------------------------------------------------------------------
-- Shift refister with serilial XOR, and reset

	USE WORK.const.ALL;
ENTITY dshr IS
PORT (clk, ce, reset, din: IN BIT;
	dout: OUT BIT_VECTOR(0 TO m-1)); 
END dshr;

ARCHITECTURE dshra OF dshr IS
	SIGNAL ring: BIT_VECTOR(0 TO m-1);
	SIGNAL dmul1: BIT;
  BEGIN
	dout<= ring;
	dmul1<= ring(m-1) XOR din;
  PROCESS BEGIN
	WAIT UNTIL clk'EVENT AND clk='1';
	IF reset='1' THEN 
	  ring(0)<= '0';
	ELSIF ce='1' THEN 
	  ring(0)<= ring(m-1) XOR din;
	END IF;	

	FOR i IN 1 TO m-1 LOOP
	  IF reset= '1' THEN
	    ring(i)<= '0';	
	  ELSIF ce='1' THEN
	    ring(i)<= ring(i-1);
	  END IF;
	END LOOP;
  END PROCESS;
END dshra;

---------------------------------------------------------------------
-- dout<= en And din

	USE WORK.const.ALL;
ENTITY dandm IS
PORT (en: IN BIT;
	din: IN BIT_VECTOR(0 TO m-1);
	dout: OUT BIT_VECTOR(0 TO m-1)); 
END dandm;

ARCHITECTURE dandma OF dandm IS
  BEGIN
	gen:
	FOR i IN 0 TO m-1 GENERATE
	  dout(i)<= din(i) AND en;
	END GENERATE;
END dandma;


---------------------------------------------------------------------
---------------------------------------------------------------------
-- buffer circuit

	USE WORK.const.ALL;
ENTITY dbuf IS
PORT (clk, bufCe, bufkCe, err, vdout1, din: IN BIT;
	dout: OUT BIT); 
END dbuf;

ARCHITECTURE dbufa OF dbuf IS
	CONSTANT buf_size: INTEGER:= 5; 
	-- buf_size= chpe/interleave + 2 if buf_size<k+1; else buf_size= k 
	SIGNAL bufk: BIT_VECTOR(0 TO k-1); 
	-- bufk - first buffor for storing only first k bits
	SIGNAL buf: BIT_VECTOR(0 TO buf_size-1); -- second buffor
  BEGIN
  PROCESS BEGIN
	WAIT UNTIL clk'EVENT AND clk='1';
	IF bufCe='1' THEN
		buf<= bufk(k-1) & buf(0 TO buf_size-2);
	END IF;
	IF bufkCe='1' THEN
		bufk<= din & bufk(0 TO k-2);
	END IF;
	dout<= (buf(buf_size-1) XOR err) AND vdout1;
  END PROCESS;
END dbufa;

-----------------------------------------------------------------
-- Bit-Serial Berlekamp (Dual Basis) Multiplier without registers

	USE WORK.const.ALL;
ENTITY dsdbm IS
PORT (dbin, sbin: IN BIT_VECTOR(0 TO m-1); -- standard & dual basis input
	dout: OUT BIT); -- serial output 
END dsdbm;

ARCHITECTURE dsdbma OF dsdbm IS
	SIGNAL dxor: BIT_VECTOR(0 TO m-1); -- xor gates signals
  BEGIN
	dout<= dxor(m-1);
	dxor(0)<= sbin(0) AND dbin(0);
	gen:
	FOR i IN 1 TO m-1 GENERATE
	  dxor(i)<= dxor(i-1) XOR (sbin(i) AND dbin(i));
	END GENERATE;
END dsdbma;

-----------------------------------------------------------------
--  Bit-Serial Berlekamp (Dual Basis) Multiplier LFSR

	USE WORK.const.ALL;
ENTITY dsdbmRing IS
PORT (clk, pe: IN BIT;   -- pe- parellel enable
	din: IN BIT_VECTOR(0 TO m-1); -- dual basis input
	dout: OUT BIT_VECTOR(0 TO m-1)); 
END dsdbmRing;

ARCHITECTURE dsdbmRinga OF dsdbmRing IS
	SIGNAL ring: BIT_VECTOR(0 TO m-1); 
  BEGIN
	dout<= ring;
  PROCESS BEGIN
	WAIT UNTIL clk'EVENT AND clk='1';
	IF pe='1' THEN 
	  ring<= din;
	ELSE
	  ring(0 TO m-2)<= ring(1 TO m-1);
	  ring(m-1)<= ring(0) XOR ring(1);
	END IF;
  END PROCESS;
END dsdbmRinga;

-------------------------------------------------------------------
-- Bit-Parallel Dual-Basis Multiplier

	USE WORK.const.ALL;
ENTITY dpdbm IS
PORT (ddin, dsin: IN BIT_VECTOR(0 TO m-1); 
	dout: OUT BIT_VECTOR(0 TO m-1));  
END dpdbm;

ARCHITECTURE dpdbma OF dpdbm IS
	COMPONENT dsdbm -- Serial Dual Basis Multiplier without registers
	  PORT (dbin, sbin: IN BIT_VECTOR(0 TO m-1); 
	  	  -- dual & standard basis in
		dout: OUT BIT); 
	  END COMPONENT;
	  FOR ALL: dsdbm USE ENTITY WORK.dsdbm (dsdbma);

	SIGNAL aux: BIT_VECTOR(0 TO m-2); -- auxuliary signals
	SIGNAL m0in, m1in, m2in, m3in: BIT_VECTOR(0 TO m-1);
  BEGIN
	aux(0)<= ddin(0) XOR ddin(1);
	aux(1)<= ddin(1) XOR ddin(2);
	aux(2)<= ddin(2) XOR ddin(3);
	m0in<= ddin(0) & ddin(1) & ddin(2) & ddin(3);
	m1in<= ddin(1) & ddin(2) & ddin(3) & aux(0);
	m2in<= ddin(2) & ddin(3) & aux(0) & aux(1);
	m3in<= ddin(3) & aux(0) & aux(1) & aux(2);
	m0:  dsdbm
		PORT MAP (m0in, dsin, dout(0));
	m1:  dsdbm
		PORT MAP (m1in, dsin, dout(1));
	m2:  dsdbm
		PORT MAP (m2in, dsin, dout(2));
	m3:  dsdbm
		PORT MAP (m3in, dsin, dout(3));

END dpdbma; 

-------------------------------------------------------------------
-- Bit-Parallel Multiplier 

	USE WORK.const.ALL;
ENTITY dpm IS
PORT (din1, din2: IN BIT_VECTOR(0 TO m-1); 
	dout: OUT BIT_VECTOR(0 TO m-1));  
END dpm;

ARCHITECTURE dpma OF dpm IS
	COMPONENT dsdbm -- Serial Dual Basis Multiplier without registers
	  PORT (dbin, sbin: IN BIT_VECTOR(0 TO m-1); 
	  	  -- dual & standard basis in
		dout: OUT BIT); 
	  END COMPONENT;
	  FOR ALL: dsdbm USE ENTITY WORK.dsdbm (dsdbma);

	SIGNAL b: BIT_VECTOR(0 TO 6);
	SIGNAL c0, c1, c2, c3: BIT_VECTOR(0 TO m-1);
  BEGIN
	b(0 TO m-1)<= din1;
	b(4)<= b(0) XOR b(3);
	b(5)<= b(3) XOR b(2);
	b(6)<= b(2) XOR b(1);
	c0<= b(0) & b(3) & b(2) & b(1);
	m0: dsdbm
		PORT MAP (din2, c0, dout(0));
	c1<= b(1) & b(4) & b(5) & b(6);
	m1: dsdbm
		PORT MAP (din2, c1, dout(1));
	c2<= b(2) & b(1) & b(4) & b(5);
	m2: dsdbm
		PORT MAP (din2, c2, dout(2));
	c3<= b(3) & b(2) & b(1) & b(4);
	m3: dsdbm
		PORT MAP (din2, c3, dout(3));

END dpma;

----------------------------------------------------------------------------------
-- Bit-Serial Standard Basis Multiplier for syn*c=dr module2 - ring

	USE WORK.const.ALL;
ENTITY dssbm IS
PORT (clk, ce, pe : IN BIT;
	din: IN BIT_VECTOR(0 TO m-1); 
	dout: OUT BIT_VECTOR(0 TO m-1)); 
END dssbm;

ARCHITECTURE dssbma OF dssbm IS
	SIGNAL ring: BIT_VECTOR(0 TO m-1);
  BEGIN
	dout<= ring;
  PROCESS BEGIN
      WAIT UNTIL clk'EVENT AND clk='1';
      IF pe='1' THEN 
	ring<= din;
      ELSIF ce='1' THEN
	ring(0)<= din(0) XOR (NOT pe AND ring(m-1));
	ring(1)<= din(1) XOR (NOT pe AND (ring(m-1) XOR ring(0)));
	ring(2)<= din(2) XOR (NOT pe AND ring(1));
	ring(3)<= din(3) XOR (NOT pe AND ring(2));
      END IF;
  END PROCESS;
END dssbma;	

-------------------------------------------------------------------
-- sumator t* XOR - dout= din(0) xor din(1) .... xor din(t)

	USE WORK.const.ALL;
ENTITY dxort IS
PORT (din0, din1, din2, din3: IN BIT;
	dout: OUT BIT);
END dxort;

ARCHITECTURE dxorta OF dxort IS
  BEGIN
	dout<= din0 XOR din1 XOR din2 XOR din3;