📄 fredevider.vhd
字号:
library ieee;
use ieee.std_logic_1164.all;
entity fredevider is
port
(clkin:in std_logic;
clkout:out std_logic);
end;
architecture b_fredevider of fredevider is
constant n:integer:=3;
signal counter:integer range 0 to n;
signal clk:std_logic;
begin
process(clkin)
begin
if rising_edge(clkin) then
if counter=n then
counter<=0;
clk<=not clk;
else
counter<=counter+1;
end if;
end if;
end process;
clkout<=clk;
end;
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -