📄 display.vhd
字号:
library ieee;
use ieee.std_logic_1164.all;
entity display is
port
(clk:in std_logic;
shanshuo:in std_logic;
num:in integer range 0 to 15;
display:out std_logic_vector(0 to 6));
end;
architecture b_display of display is
signal timeout:integer range 0 to 63;
begin
process(clk)
begin
if rising_edge(clk) then
if(shanshuo='0') then
timeout<=0;
else
if (timeout=63) then
timeout<=0;
else
timeout<=timeout+1;
end if;
end if;
if (timeout=31) then
case num is
when 0=>display<="1111110";
when 1=>display<="0110000";
when 2=>display<="1101101";
when 3=>display<="1111001";
when 4=>display<="0110011";
when 5=>display<="1011011";
when 6=>display<="0011111";
when 7=>display<="1110000";
when 8=>display<="1111111";
when 9=>display<="1110011";
when others=>display<="0000000";
end case;
else
display<="0000000";
end if;
end if;
end process;
end;
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -