📄 counter.vhd
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library ieee;
use ieee.std_logic_1164.all;
entity counter is
port
(clk:in std_logic;
hold: in std_logic;
reset: in std_logic;
num: buffer integer range 0 to 49);
end;
architecture b_counter of counter is
begin
process(clk,reset)
begin
if reset='1' then
num<=0;
elsif rising_edge(clk) then
if hold='1' then
num<=num;
else
if num=49 then
num<=0;
else
num<=num+1;
end if;
end if;
end if;
end process;
end b_counter;
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