hal_cache.c

某个ARM9板子的实际bootloader 对裁剪

    X_ARM_MMU_SECTION(SL2312_UART_BASE,  SL2312_UART_BASE,   1,  
    				ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW);
#endif
#ifdef SL2312_TIMER_BASE
    X_ARM_MMU_SECTION(SL2312_TIMER_BASE,  SL2312_TIMER_BASE,   1,  
    				ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW);
#endif
#ifdef SL2312_LCD_BASE
    X_ARM_MMU_SECTION(SL2312_LCD_BASE,  SL2312_LCD_BASE,   1,  
    				ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW);
#endif
#ifdef SL2312_RTC_BASE
    X_ARM_MMU_SECTION(SL2312_RTC_BASE,  SL2312_RTC_BASE,   1,  
    				ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW);
#endif
#ifdef SL2312_SATA_BASE
    X_ARM_MMU_SECTION(SL2312_SATA_BASE,  SL2312_SATA_BASE,   1,  
    				ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW);
#endif
#ifdef SL2312_LPC_HOST_BASE
    X_ARM_MMU_SECTION(SL2312_LPC_HOST_BASE,  SL2312_LPC_HOST_BASE,   1,  
    				ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW);
#endif
#ifdef SL2312_LPC_IO_BASE
    X_ARM_MMU_SECTION(SL2312_LPC_IO_BASE,  SL2312_LPC_IO_BASE,   1,  
    				ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW);
#endif
#ifdef SL2312_INTERRUPT_BASE
    X_ARM_MMU_SECTION(SL2312_INTERRUPT_BASE,  SL2312_INTERRUPT_BASE,   1,  
    				ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW);
#endif
#ifdef SL2312_INTERRUPT1_BASE
    X_ARM_MMU_SECTION(SL2312_INTERRUPT1_BASE,  SL2312_INTERRUPT1_BASE,   1,  
    				ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW);
#endif
#ifdef SL2312_SSP_CTRL_BASE
    X_ARM_MMU_SECTION(SL2312_SSP_CTRL_BASE,  SL2312_SSP_CTRL_BASE,   1,  
    				ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW);
#endif
#ifdef SL2312_POWER_CTRL_BASE
    X_ARM_MMU_SECTION(SL2312_POWER_CTRL_BASE,  SL2312_POWER_CTRL_BASE,   1,  
    				ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW);
#endif
#ifdef SL2312_CIR_BASE
    X_ARM_MMU_SECTION(SL2312_CIR_BASE,  SL2312_CIR_BASE,   1,  
    				ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW);
#endif
#ifdef SL2312_GPIO_BASE
    X_ARM_MMU_SECTION(SL2312_GPIO_BASE,  SL2312_GPIO_BASE,   1,  
    				ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW);
#endif
#ifdef SL2312_GPIO_BASE1
    X_ARM_MMU_SECTION(SL2312_GPIO_BASE1,  SL2312_GPIO_BASE1,   1,  
    				ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW);
#endif
#ifdef SL2312_GPIO_BASE2
    X_ARM_MMU_SECTION(SL2312_GPIO_BASE2,  SL2312_GPIO_BASE2,   1,  
    				ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW);
#endif
#ifdef SL2312_PCI_IO_BASE
    X_ARM_MMU_SECTION(SL2312_PCI_IO_BASE,  SL2312_PCI_IO_BASE,   1,  
    				ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW);
#endif
#ifdef SL2312_PCI_MEM_BASE
    X_ARM_MMU_SECTION(SL2312_PCI_MEM_BASE,  SL2312_PCI_MEM_BASE,   128,  
    				ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW);
#endif
#ifdef SL2312_GMAC0_BASE
    X_ARM_MMU_SECTION(SL2312_GMAC0_BASE,  SL2312_GMAC0_BASE,   1,  
    				ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW);
#endif
#ifdef SL2312_GMAC1_BASE
    X_ARM_MMU_SECTION(SL2312_GMAC1_BASE,  SL2312_GMAC1_BASE,   1,  
    				ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW);
#endif
#ifdef SL2312_EMAC_BASE
    X_ARM_MMU_SECTION(SL2312_EMAC_BASE,  SL2312_EMAC_BASE,   1,  
    				ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW);
#endif
#ifdef SL2312_SECURITY_BASE
    X_ARM_MMU_SECTION(SL2312_SECURITY_BASE,  SL2312_SECURITY_BASE,   1,  
    				ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW);
#endif
#ifdef SL2312_IDE_BASE
    X_ARM_MMU_SECTION(SL2312_IDE_BASE,  SL2312_IDE_BASE,   1,  
    				ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW);
#endif
#ifdef SL2312_IDE0_BASE
    X_ARM_MMU_SECTION(SL2312_IDE0_BASE,  SL2312_IDE0_BASE,   128,  
    				ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW);
#endif
//#ifdef SL2312_IDE1_BASE
//    X_ARM_MMU_SECTION(SL2312_IDE1_BASE,  SL2312_IDE1_BASE,   1,  
//    				ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW);
//#endif
#ifdef SL2312_RAID_BASE
    X_ARM_MMU_SECTION(SL2312_RAID_BASE,  SL2312_RAID_BASE,   128,  
    				ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW);
#endif
#ifdef SL2312_FLASH_CTRL_BASE
    X_ARM_MMU_SECTION(SL2312_FLASH_CTRL_BASE,  SL2312_FLASH_CTRL_BASE,   1,  
    				ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW);
#endif
#ifdef SL2312_DRAM_CTRL_BASE
    X_ARM_MMU_SECTION(SL2312_DRAM_CTRL_BASE,  SL2312_DRAM_CTRL_BASE,   1,  
    				ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW);
#endif
#ifdef SL2312_GENERAL_DMA_BASE
    X_ARM_MMU_SECTION(SL2312_GENERAL_DMA_BASE,  SL2312_GENERAL_DMA_BASE,   1,  
    				ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW);
#endif
#ifdef SL2312_USB_BASE
    X_ARM_MMU_SECTION(SL2312_USB_BASE,  SL2312_USB_BASE,   1,  
    				ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW);
#endif
#ifdef SL2312_USB0_BASE
    X_ARM_MMU_SECTION(SL2312_USB0_BASE,  SL2312_USB0_BASE,   1,  
    				ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW);
#endif
#ifdef SL2312_USB1_BASE
    X_ARM_MMU_SECTION(SL2312_USB1_BASE,  SL2312_USB1_BASE,   1,  
    				ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW);
#endif
#endif // 0
}

/*----------------------------------------------------------------------
* hal_get_mmu_status
*----------------------------------------------------------------------*/
int hal_get_mmu_status(void)
{
    int mmu;
	
	asm volatile (	
		"mrc p15,0,%0,c1,c0,0;"
        "nop;"
        "nop;"
        "nop;"
        :"=r"(mmu)	/* output */
        :					/* input */
        //:"r0"				/* affected registers */
	);
	
 	return (mmu & 0x0001) ? 1 : 0;
}

/*----------------------------------------------------------------------
* hal_get_icache_status
*----------------------------------------------------------------------*/
int hal_get_icache_status(void)
{
    int mmu;
	
	asm volatile (	
		"mrc p15,0,%0,c1,c0,0;"
        "nop;"
        "nop;"
        "nop;"
        :"=r"(mmu)	/* output */
        :					/* input */
        //:"r0"				/* affected registers */
	);
	
 	return (mmu & 0x1000) ? 1 : 0;
}

/*----------------------------------------------------------------------
* hal_get_dcache_status
*----------------------------------------------------------------------*/
int hal_get_dcache_status(void)
{
    int mmu;
	
	asm volatile (	
		"mrc p15,0,%0,c1,c0,0;"
        "nop;"
        "nop;"
        "nop;"
        :"=r"(mmu)	/* output */
        :					/* input */
        //:"r0"				/* affected registers */
	);
	
 	return (mmu & 0x0004) ? 1 : 0;
}


/*----------------------------------------------------------------------
* hal_set_icache
*	i/p: 1: enable, 0: disable
*----------------------------------------------------------------------*/
int hal_set_icache(int flag)
{
    int mmu;
	
	asm volatile (	
		"mrc p15,0,%0,c1,c0,0;"
        "nop;"
        "nop;"
        "nop;"
        :"=r"(mmu)	/* output */
        :					/* input */
        //:"r0"				/* affected registers */
	);
	
 	return (mmu & 0x1000) ? 1 : 0;
}