emac_diag.c

某个ARM9板子的实际bootloader 对裁剪

	txdma_ctrl_mask.bits.td_bus = 1;
	txdma_ctrl_mask.bits.td_endian = 1;
	txdma_ctrl_mask.bits.td_finish_en = 1;
	txdma_ctrl_mask.bits.td_fail_en = 1;
	txdma_ctrl_mask.bits.td_perr_en = 1;
	txdma_ctrl_mask.bits.td_eod_en = 1;
	txdma_ctrl_mask.bits.td_eof_en = 1;
	emac_write_reg(EMAC_TXDMA_CTRL,txdma_ctrl.bits32,txdma_ctrl_mask.bits32);
	
    /* program rx dma control register */	
	rxdma_ctrl.bits32 = 0;
	rxdma_ctrl.bits.rd_start = 1;    /* start RX DMA transfer */
	rxdma_ctrl.bits.rd_continue = 1; /* continue RX DMA operation */
	rxdma_ctrl.bits.rd_chain_mode = 1;   /* chain mode */
	rxdma_ctrl.bits.rd_prot = 0;
	rxdma_ctrl.bits.rd_burst_size = 2;
	rxdma_ctrl.bits.rd_bus = 0;
	rxdma_ctrl.bits.rd_endian = 0;
	rxdma_ctrl.bits.rd_finish_en = 1;
	rxdma_ctrl.bits.rd_fail_en = 1;
	rxdma_ctrl.bits.rd_perr_en = 1;
	rxdma_ctrl.bits.rd_eod_en = 0; /* disable Rx End of Descriptor Interrupt */
	rxdma_ctrl.bits.rd_eof_en = 1;
	rxdma_ctrl_mask.bits32 = 0;
	rxdma_ctrl_mask.bits.rd_start = 1;    
	rxdma_ctrl_mask.bits.rd_continue = 1; 
	rxdma_ctrl_mask.bits.rd_chain_mode = 1;
	rxdma_ctrl_mask.bits.rd_prot = 15;
	rxdma_ctrl_mask.bits.rd_burst_size = 3;
	rxdma_ctrl_mask.bits.rd_bus = 1;
	rxdma_ctrl_mask.bits.rd_endian = 1;
	rxdma_ctrl_mask.bits.rd_finish_en = 1;
	rxdma_ctrl_mask.bits.rd_fail_en = 1;
	rxdma_ctrl_mask.bits.rd_perr_en = 1;
	rxdma_ctrl_mask.bits.rd_eod_en = 1;
	rxdma_ctrl_mask.bits.rd_eof_en = 1;
	emac_write_reg(EMAC_RXDMA_CTRL,rxdma_ctrl.bits32,rxdma_ctrl_mask.bits32);
    return;	
}	

/*----------------------------------------------------------------------
* emac_diag_hw_stop
*----------------------------------------------------------------------*/
void emac_diag_hw_stop(void)
{
    EMAC_TXDMA_CTRL_T       txdma_ctrl,txdma_ctrl_mask;
    EMAC_RXDMA_CTRL_T       rxdma_ctrl,rxdma_ctrl_mask;

    /* program tx dma control register */	
	txdma_ctrl.bits32 = 0;
	txdma_ctrl.bits.td_start = 0;    
	txdma_ctrl.bits.td_continue = 0; 
	txdma_ctrl_mask.bits32 = 0;
	txdma_ctrl_mask.bits.td_start = 1;    
	txdma_ctrl_mask.bits.td_continue = 1; 	
	emac_write_reg(EMAC_TXDMA_CTRL,txdma_ctrl.bits32,txdma_ctrl_mask.bits32);
    /* program rx dma control register */	
	rxdma_ctrl.bits32 = 0;
	rxdma_ctrl.bits.rd_start = 0;    /* stop RX DMA transfer */
	rxdma_ctrl.bits.rd_continue = 0; /* stop continue RX DMA operation */
	rxdma_ctrl_mask.bits32 = 0;
	rxdma_ctrl_mask.bits.rd_start = 1;    
	rxdma_ctrl_mask.bits.rd_continue = 1; 
	emac_write_reg(EMAC_RXDMA_CTRL,rxdma_ctrl.bits32,rxdma_ctrl_mask.bits32);
}

/*----------------------------------------------------------------------
* emac_diag_rx_isr_begin
*----------------------------------------------------------------------*/
static void emac_diag_rx_isr_begin(EMAC_INFO_T *tpp)
{
	int                    tx_tmptail;
	int					  total=0;	// gary
  EMAC_TXDMA_FIRST_DESC_T txdma_busy;
  EMAC_TXDMA_CTRL_T       tx_ctrl,tx_ctrl_mask;
#ifdef EMAC_DIAG_ENABLE_FLOW_CTRL	
	unsigned int	desc_count; 
#endif
	BD_FRAME_CTRL_T	reg_desc_frame_ctrl;
	unsigned int		reg_desc_buf_adr;
	BD_FLAG_STATUS_T	reg_desc_flag_status;
	BD_NEXT_DESC_T	reg_desc_next_desc;
  
#ifdef	DIAG_BY_LA
	{
		unsigned long data;
		data = REG32(SL2312_FLASH_SHADOW);
	}
#endif

  tx_tmptail = tpp->tx_tail;
  // copy rx_desc[tpp->rx_head] to reg_desc
  reg_desc_frame_ctrl.bits32  
    = tpp->rx_desc[tpp->rx_head].frame_ctrl.bits32 ;
  while ( reg_desc_frame_ctrl.bits_rx.own == CPU && tpp->rx_head != -1)
  {
  	reg_desc_flag_status.bits32  
    	= tpp->rx_desc[tpp->rx_head].flag_status.bits32 ;
  	reg_desc_buf_adr  
    	= tpp->rx_desc[tpp->rx_head].buf_adr ;
  	reg_desc_next_desc.next_descriptor  
    	= tpp->rx_desc[tpp->rx_head].next_desc.next_descriptor;

  	total++;
#ifdef EMAC_STATISTICS		
  	tpp->rx_pkts++;
#endif
#if 0   
   	if (reg_desc_flag_status.bits32 == 0)
   	{
   		tpp->tx_err++;
   		printf("err: reg_desc_frame_ctrl=0x%x, reg_desc_flag_status=0x%x, tpp->tx_desc[tx_tmptail].frame_ctrl.bits32=0x%x\n", 
   				reg_desc_frame_ctrl.bits32, reg_desc_flag_status.bits32, tpp->tx_desc[tx_tmptail].frame_ctrl.bits32);
   	}
#endif   	
    // reg_desc_frame_ctrl.bits32 &= 0x0000ffff;
    if ( tx_tmptail != tpp->tx_tail )
      reg_desc_frame_ctrl.bits32 = 0x80000000 + reg_desc_flag_status.bits_rx_status.frame_count-4;		// DMA bit
    else
      reg_desc_frame_ctrl.bits32 = reg_desc_flag_status.bits_rx_status.frame_count-4;		// DMA bit
    
	// setup tx descriptor and rd_index
    tpp->tx_desc[tx_tmptail].frame_ctrl.bits32 						// Gary Mask 
      = reg_desc_frame_ctrl.bits32;								// Gary Mask 
    tpp->tx_desc[tx_tmptail].flag_status.bits32  					// Gary Mask 
      = reg_desc_flag_status.bits_rx_status.frame_count-4;
    // tpp->tx_desc[tx_tmptail].frame_ctrl.bits_tx.buffer_size =			// Gary Add
    //tpp->tx_desc[tx_tmptail].flag_status.bits_tx_flag.frame_count		// Gary Add
    //  = reg_desc_flag_status.bits_rx_status.frame_count-4;			// Gary Add
    tpp->tx_desc[tx_tmptail].buf_adr  
      = reg_desc_buf_adr ;

#if 0   
   	if (tpp->tx_desc[tx_tmptail].frame_ctrl.bits32 == 0x7ffffffc)
   	{
   		tpp->tx_err++;
   		printf("err: reg_desc_frame_ctrl=0x%x, reg_desc_flag_status=0x%x, tpp->tx_desc[tx_tmptail].frame_ctrl.bits32=0x%x\n", 
   				reg_desc_frame_ctrl.bits32, reg_desc_flag_status.bits32, tpp->tx_desc[tx_tmptail].frame_ctrl.bits32);
   	}
#endif   	
    tpp->rd_index[tx_tmptail] = tpp->rx_head;

#ifdef EMAC_DIAG_ENABLE_FLOW_CTRL
	desc_count = reg_desc_frame_ctrl.bits_rx.desc_count; /* get descriptor count per frame */
	emac_write_reg(EMAC_BNCR, desc_count, 0x0000ffff);
#endif

	// advance tx_tmptail
    tx_tmptail = (tx_tmptail+1)%TX_DESC_NUM;
	// advance rx_head
	if ((reg_desc_next_desc.next_descriptor & ~0x0f))
    	tpp->rx_head = ((unsigned int)(reg_desc_next_desc.next_descriptor & 0xfffffff0)
                 - (unsigned int)tpp->rx_desc)
                 / sizeof(EMAC_DESCRIPTOR_T);
    else
    {
    	tpp->rx_head = -1;
    	break;
    }
    	

	// read tpp->rx_desc[tpp->rx_head] to reg_desc
    //reg_desc_frame_ctrl.bits32						// Gary mask
    //  = tpp->rx_desc[tpp->rx_head].frame_ctrl.bits32 ;	// Gary mask
    reg_desc_frame_ctrl.bits32							
      = tpp->rx_desc[tpp->rx_head].frame_ctrl.bits32 ;		
  }
  		
#ifdef	DIAG_BY_LA
	{
		unsigned long data;
		data = REG32(SL2312_FLASH_SHADOW);
	}
#endif

  // if ( tx_tmptail != tpp->tx_tail )
  if ( total || (tpp->rx_head == -1))
  {  // packet need to transmitted.
  	// REG8(tpp->tx_desc[tpp->tx_tail].buf_adr) = 0x22; /* Gary testing */
    tpp->tx_desc[tpp->tx_tail].frame_ctrl.bits_tx.own = DMA;
    tpp->tx_tail = tx_tmptail;								// Gary add
    txdma_busy.bits32 = emac_read_reg(EMAC_TXDMA_FIRST_DESC);
    if (txdma_busy.bits.td_busy == 0)
    {
	  emac_write_reg(EMAC_TXDMA_CURR_DESC,(unsigned int)(&tpp->tx_desc[tpp->tx_head]) | 0x0b,0xffffffff);
	  emac_write_reg(0xff2c,(unsigned int)(&tpp->tx_desc[tpp->tx_head]) | 0x0b,0xffffffff);   /* rx next descriptor address */
      /* restart DMA process */
      tx_ctrl.bits32 = 0;
      tx_ctrl.bits.td_start = 1;
      tx_ctrl.bits.td_continue = 1;
      tx_ctrl_mask.bits32 = 0;
      tx_ctrl_mask.bits.td_start = 1;
      tx_ctrl_mask.bits.td_continue = 1;
      emac_write_reg(EMAC_TXDMA_CTRL,tx_ctrl.bits32,tx_ctrl_mask.bits32);
    }
  }
}

/*----------------------------------------------------------------------
* emac_diag_tx_isr_begin
*----------------------------------------------------------------------*/
static void emac_diag_tx_isr_begin(EMAC_INFO_T *tpp)
{
  // register EMAC_DESCRIPTOR_T       reg_desc;
	int                     rx_tmphead, rx_tmptail;
	int                     reg_rxdesc_index;
  EMAC_RXDMA_FIRST_DESC_T rxdma_busy;
  EMAC_RXDMA_CTRL_T       rxdma_ctrl,rxdma_ctrl_mask;
	BD_FRAME_CTRL_T	reg_desc_frame_ctrl;
	unsigned int		reg_desc_buf_adr;
	BD_FLAG_STATUS_T	reg_desc_flag_status;
	BD_NEXT_DESC_T	reg_desc_next_desc;

  rx_tmphead = -1;
  rx_tmptail = -1;
  // copy tx_desc[tp.tx_head] to reg_desc
  reg_desc_frame_ctrl.bits32  
    = tpp->tx_desc[tpp->tx_head].frame_ctrl.bits32 ;
  reg_desc_flag_status.bits32  
    = tpp->tx_desc[tpp->tx_head].flag_status.bits32 ;
  reg_desc_buf_adr  
    = tpp->tx_desc[tpp->tx_head].buf_adr ;
  reg_desc_next_desc.next_descriptor  
    = tpp->tx_desc[tpp->tx_head].next_desc.next_descriptor;
  reg_rxdesc_index = tpp->rd_index[tpp->tx_head];

  // while (reg_desc_frame_ctrl.bits_tx.own == CPU )	// Gary Mask
  // while (reg_desc_frame_ctrl.bits_tx.own == CPU && reg_desc_frame_ctrl.bits_tx.success_tx)	// Gary change
  while (reg_desc_frame_ctrl.bits_tx.own == CPU && tpp->tx_head != tpp->tx_tail)
  {
  	// tpp->tx_desc[tpp->tx_head].frame_ctrl.bits_tx.success_tx = 0;
#ifdef EMAC_STATISTICS		
     tpp->tx_pkts++;
#endif 	
	if ( rx_tmphead == -1 )
	  rx_tmphead = reg_rxdesc_index;
	if ( rx_tmptail != -1 )
      tpp->rx_desc[rx_tmptail].next_desc.next_descriptor
		= (unsigned int)&tpp->rx_desc[reg_rxdesc_index] | 0x0000000b;

	rx_tmptail = reg_rxdesc_index;
    tpp->tx_head = (tpp->tx_head + 1) % TX_DESC_NUM;

	// Init tpp->rx_desc[reg_rx_desc_index];
    reg_desc_buf_adr            = (unsigned int)tpp->bufs + reg_rxdesc_index * RX_BUF_SIZE;
    reg_desc_frame_ctrl.bits32  = 0x80000000 | RX_BUF_SIZE;		// GARYCHEN
    tpp->rx_desc[reg_rxdesc_index].flag_status.bits32  
      = 0x00000000;
    tpp->rx_desc[reg_rxdesc_index].buf_adr
	  = reg_desc_buf_adr;
    tpp->rx_desc[reg_rxdesc_index].frame_ctrl.bits32  
      = reg_desc_frame_ctrl.bits32;

	// copy tpp->tx_desc[tpp->tx_head] to reg_desc_
    // reg_desc_frame_ctrl.bits32  						// Gary mask
    //   = tpp->tx_desc[tpp->tx_head].frame_ctrl.bits32 ;	// Gary mask
    reg_desc_flag_status.bits32  
      = tpp->tx_desc[tpp->tx_head].flag_status.bits32 ;
    reg_desc_buf_adr  
      = tpp->tx_desc[tpp->tx_head].buf_adr ;
    reg_desc_next_desc.next_descriptor  
      = tpp->tx_desc[tpp->tx_head].next_desc.next_descriptor;
    reg_rxdesc_index = tpp->rd_index[tpp->tx_head];
    reg_desc_frame_ctrl.bits32  						// Gary add
       = tpp->tx_desc[tpp->tx_head].frame_ctrl.bits32 ;		// Gary add
  }
	if ( rx_tmptail != -1 )
		tpp->rx_desc[rx_tmptail].next_desc.next_descriptor = 0 | 0x0000000b;

  if ( rx_tmphead != -1 )
  {
	if (tpp->rx_head != -1)
	{
    	tpp->rx_desc[tpp->rx_tail].next_desc.next_descriptor
	  		= (unsigned int)&tpp->rx_desc[rx_tmphead] | 0x0000000b;
		tpp->rx_tail = rx_tmptail;
	}
	else
	{
		tpp->rx_head = rx_tmphead;
		tpp->rx_tail = rx_tmptail;
	}

    rxdma_busy.bits32 = emac_read_reg(EMAC_RXDMA_FIRST_DESC) ;
    if (rxdma_busy.bits.rd_busy == 0)
    {
      /* restart Rx DMA process */
	  emac_write_reg(EMAC_RXDMA_CURR_DESC,(unsigned int)(&tpp->rx_desc[tpp->rx_head]) | 0x0b,0xffffffff);
	  emac_write_reg(0xff3c,(unsigned int)(&tpp->rx_desc[tpp->rx_head]) | 0x0b,0xffffffff);   /* rx next descriptor address */
      rxdma_ctrl.bits32 = 0;
      rxdma_ctrl.bits.rd_start = 1;    /* start RX DMA transfer */
      rxdma_ctrl.bits.rd_continue = 1; /* continue RX DMA operation */
      rxdma_ctrl_mask.bits32 = 0;
      rxdma_ctrl_mask.bits.rd_start = 1;   
      rxdma_ctrl_mask.bits.rd_continue = 1; 
      emac_write_reg(EMAC_RXDMA_CTRL,rxdma_ctrl.bits32,rxdma_ctrl_mask.bits32);
    }
  }
}

/*----------------------------------------------------------------------
* emac_diag_isr
*----------------------------------------------------------------------*/
static void emac_diag_isr(void)
{
	register unsigned long status;
	register EMAC_INFO_T *tpp;
		
	sl2312_eth_disable_interrupt();
		
	tpp = (EMAC_INFO_T *)&emac_private_data;
#ifdef EMAC_STATISTICS		
	tpp->interrupt_cnt++;
#endif	
	status = emac_read_reg(EMAC_DMA_STATUS);

	/* clear DMA status */
	emac_write_reg(EMAC_DMA_STATUS, status, status);	
        
	if (status & 0xc000)	// rx_overrun and tx_underrun bits
	{
		if (status & 0x8000)	// rx_overrun
		{
			EMAC_RXDMA_FIRST_DESC_T	rxdma_busy;
		    /* if RX DMA process is stoped , restart it */    
		    rxdma_busy.bits32 = emac_read_reg(EMAC_RXDMA_FIRST_DESC) ;
		    if (rxdma_busy.bits.rd_busy == 0)
		    {
		    	register EMAC_RXDMA_CTRL_T rxdma_ctrl,rxdma_ctrl_mask;
		    	
		        /* restart Rx DMA process */
		        if (tpp->rx_head != -1)
		        {
	  				emac_write_reg(EMAC_RXDMA_CURR_DESC,(unsigned int)(&tpp->rx_desc[tpp->rx_head]) | 0x0b,0xffffffff);
	  		    	emac_write_reg(0xff3c,(unsigned int)(&tpp->rx_desc[tpp->rx_head]) | 0x0b,0xffffffff);   /* rx next descriptor address */
	  		    }
		        rxdma_ctrl.bits32 = 0;
		        rxdma_ctrl.bits.rd_start = 1;    /* start RX DMA transfer */
		        rxdma_ctrl.bits.rd_continue = 1; /* continue RX DMA operation */
		        rxdma_ctrl_mask.bits32 = 0;
		        rxdma_ctrl_mask.bits.rd_start = 1;   
		        rxdma_ctrl_mask.bits.rd_continue = 1; 
		        emac_write_reg(EMAC_RXDMA_CTRL,rxdma_ctrl.bits32,rxdma_ctrl_mask.bits32);
		    }
#ifdef EMAC_STATISTICS		
		    tpp->rx_overrun++;
#endif		    
		}
		if (status & 0x4000)	// tx_underrun
		{
			EMAC_TXDMA_FIRST_DESC_T	txdma_busy;
#ifdef EMAC_STATISTICS		
		    tpp->tx_underrun++;
#endif
		    /* if TX DMA process is stoped , restart it */    
		    txdma_busy.bits32 = emac_read_reg(EMAC_TXDMA_FIRST_DESC);
		    if (txdma_busy.bits.td_busy == 0)
		    {
		    	register EMAC_TXDMA_CTRL_T txdma_ctrl,txdma_ctrl_mask;
		    	
		        /* restart Tx DMA process */
	  			emac_write_reg(EMAC_TXDMA_CURR_DESC,(unsigned int)(&tpp->tx_desc[tpp->tx_head]) | 0x0b,0xffffffff);
	  			emac_write_reg(0xff2c,(unsigned int)(&tpp->tx_desc[tpp->tx_head]) | 0x0b,0xffffffff);   /* rx next descriptor address */
		        txdma_ctrl.bits32 = 0;
		        txdma_ctrl.bits.td_start = 1;
		        txdma_ctrl.bits.td_continue = 1;
		        txdma_ctrl_mask.bits32 = 0;
		        txdma_ctrl_mask.bits.td_start = 1;
		        txdma_ctrl_mask.bits.td_continue = 1;
		        emac_write_reg(EMAC_TXDMA_CTRL,txdma_ctrl.bits32,txdma_ctrl_mask.bits32);
		    }
		}
	}
	else
	{	    
		/* receive rx interrupt */
    	if (status & 0x04C00000)	// rs_eofi, rs_eodi, and rs_finish
    	{
#ifdef EMAC_STATISTICS		
    		tpp->rx_intr_cnt++;
#endif
			emac_diag_rx_isr_begin(tpp);
		}
	        
		/* receive tx interrupt */
		if (status & 0x98000000)	// ts_eofi, ts_finish, and ts_eodi bits
		{
#ifdef EMAC_STATISTICS		
    		tpp->tx_intr_cnt++;
#endif
			emac_diag_tx_isr_begin(tpp);
		}
	}
    	
	sl2312_eth_enable_interrupt();
	return;
}

#endif // MIDWAY