gmac_sl2312.h
来自「某个ARM9板子的实际bootloader 对裁剪」· C头文件 代码 · 共 750 行 · 第 1/2 页
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750 行
unsigned int m_rx_pause_on : 1; /* received pause on frame interrupt mask */ unsigned int m_tx_pause_on : 1; /* transmit pause on frame interrupt mask */ unsigned int m_rx_pause_off : 1; /* received pause off frame interrupt mask */ unsigned int m_tx_pause_off : 1; /* received pause off frame interrupt mask */ unsigned int m_rx_overrun : 1; /* GMAC Rx FIFO overrun interrupt mask */ unsigned int m_link_change : 1; /* GMAC link changed Interrupt mask for RGMII mode */#else unsigned int m_link_change : 1; /* GMAC link changed Interrupt mask for RGMII mode */ unsigned int m_rx_overrun : 1; /* GMAC Rx FIFO overrun interrupt mask */ unsigned int m_tx_pause_off : 1; /* received pause off frame interrupt mask */ unsigned int m_rx_pause_off : 1; /* received pause off frame interrupt mask */ unsigned int m_tx_pause_on : 1; /* transmit pause on frame interrupt mask */ unsigned int m_rx_pause_on : 1; /* received pause on frame interrupt mask */ unsigned int m_cnt_full : 1; /* MIB counters half full interrupt mask */ unsigned int : 1; /* Tx fail interrupt mask */ unsigned int loop_back : 1; /* loopback TxDMA to RxDMA */ unsigned int : 3; unsigned int : 1; unsigned int : 1; unsigned int link_change : 1; /* GMAC link changed Interrupt for RGMII mode */ unsigned int rx_overrun : 1; /* GMAC Rx FIFO overrun interrupt */ unsigned int tx_pause_off : 1; /* received pause off frame interrupt */ unsigned int rx_pause_off : 1; /* received pause off frame interrupt */ unsigned int tx_pause_on : 1; /* transmit pause on frame interrupt */ unsigned int rx_pause_on : 1; /* received pause on frame interrupt */ unsigned int cnt_full : 1; /* MIB counters half full interrupt */ unsigned int : 1; /* Tx fail interrupt */ unsigned int rs_eofi : 1; /* RxDMA end of frame interrupt */ unsigned int rs_eodi : 1; /* RxDMA end of descriptor interrupt */ unsigned int rs_perr : 1; /* Rx Descriptor protocol error */ unsigned int rs_derr : 1; /* AHB Bus Error while rx */ unsigned int rs_finish : 1; /* finished rx interrupt */ unsigned int ts_eofi : 1; /* TxDMA end of frame interrupt */ unsigned int ts_eodi : 1; /* TxDMA end of descriptor interrupt */ unsigned int ts_perr : 1; /* Tx Descriptor protocol error */ unsigned int ts_derr : 1; /* AHB Bus Error while tx */ unsigned int ts_finish : 1; /* finished tx interrupt */#endif } bits;} GMAC_DMA_STATUS_T;typedef union{ unsigned int bits32; struct bit2_ff08 {#if (BIG_ENDIAN==1) unsigned int td_start : 1; /* Start DMA transfer */ unsigned int td_continue : 1; /* Continue DMA operation */ unsigned int td_chain_mode : 1; /* Descriptor Chain Mode;1-Descriptor Chain mode, 0-Direct DMA mode*/ unsigned int : 1; unsigned int td_prot : 4; /* TxDMA protection control */ unsigned int td_burst_size : 2; /* TxDMA max burst size for every AHB request */ unsigned int td_bus : 2; /* peripheral bus width;0x->8 bits,10->16 bits,11->32 bits */ unsigned int td_endian : 1; /* AHB Endian. 0-little endian; 1-big endian */ unsigned int td_finish_en : 1; /* DMA Finish Event Interrupt Enable;1-enable;0-mask */ unsigned int td_fail_en : 1; /* DMA Fail Interrupt Enable;1-enable;0-mask */ unsigned int td_perr_en : 1; /* Protocol Failure Interrupt Enable;1-enable;0-mask */ unsigned int td_eod_en : 1; /* End of Descriptor interrupt Enable;1-enable;0-mask */ unsigned int td_eof_en : 1; /* End of frame interrupt Enable;1-enable;0-mask */ unsigned int : 14;#else unsigned int : 14; unsigned int td_eof_en : 1; /* End of frame interrupt Enable;1-enable;0-mask */ unsigned int td_eod_en : 1; /* End of Descriptor interrupt Enable;1-enable;0-mask */ unsigned int td_perr_en : 1; /* Protocol Failure Interrupt Enable;1-enable;0-mask */ unsigned int td_fail_en : 1; /* DMA Fail Interrupt Enable;1-enable;0-mask */ unsigned int td_finish_en : 1; /* DMA Finish Event Interrupt Enable;1-enable;0-mask */ unsigned int td_endian : 1; /* AHB Endian. 0-little endian; 1-big endian */ unsigned int td_bus : 2; /* peripheral bus width;0x->8 bits,10->16 bits,11->32 bits */ unsigned int td_burst_size : 2; /* TxDMA max burst size for every AHB request */ unsigned int td_prot : 4; /* TxDMA protection control */ unsigned int : 1; unsigned int td_chain_mode : 1; /* Descriptor Chain Mode;1-Descriptor Chain mode, 0-Direct DMA mode*/ unsigned int td_continue : 1; /* Continue DMA operation */ unsigned int td_start : 1; /* Start DMA transfer */#endif } bits;} GMAC_TXDMA_CTRL_T;typedef union{ unsigned int bits32; struct bit2_ff0c {#if (BIG_ENDIAN==1) unsigned int td_first_des_ptr : 28;/* first descriptor address */ unsigned int td_busy : 1;/* 1-TxDMA busy; 0-TxDMA idle */ unsigned int : 3;#else unsigned int : 3; unsigned int td_busy : 1;/* 1-TxDMA busy; 0-TxDMA idle */ unsigned int td_first_des_ptr : 28;/* first descriptor address */#endif } bits;} GMAC_TXDMA_FIRST_DESC_T;typedef union{ unsigned int bits32; struct bit2_ff10 {#if (BIG_ENDIAN==1) unsigned int ndar : 28; /* next descriptor address */ unsigned int eofie : 1; /* end of frame interrupt enable */ unsigned int : 1; unsigned int sof_eof : 2;#else unsigned int sof_eof : 2; unsigned int : 1; unsigned int eofie : 1; /* end of frame interrupt enable */ unsigned int ndar : 28; /* next descriptor address */#endif } bits;} GMAC_TXDMA_CURR_DESC_T;typedef union{ unsigned int bits32; struct bit2_ff14 {#if (BIG_ENDIAN==1) unsigned int rd_start : 1; /* Start DMA transfer */ unsigned int rd_continue : 1; /* Continue DMA operation */ unsigned int rd_chain_mode : 1; /* Descriptor Chain Mode;1-Descriptor Chain mode, 0-Direct DMA mode*/ unsigned int : 1; unsigned int rd_prot : 4; /* DMA protection control */ unsigned int rd_burst_size : 2; /* DMA max burst size for every AHB request */ unsigned int rd_bus : 2; /* peripheral bus width;0x->8 bits,10->16 bits,11->32 bits */ unsigned int rd_endian : 1; /* AHB Endian. 0-little endian; 1-big endian */ unsigned int rd_finish_en : 1; /* DMA Finish Event Interrupt Enable;1-enable;0-mask */ unsigned int rd_fail_en : 1; /* DMA Fail Interrupt Enable;1-enable;0-mask */ unsigned int rd_perr_en : 1; /* Protocol Failure Interrupt Enable;1-enable;0-mask */ unsigned int rd_eod_en : 1; /* End of Descriptor interrupt Enable;1-enable;0-mask */ unsigned int rd_eof_en : 1; /* End of frame interrupt Enable;1-enable;0-mask */ unsigned int : 14;#else unsigned int : 14; unsigned int rd_eof_en : 1; /* End of frame interrupt Enable;1-enable;0-mask */ unsigned int rd_eod_en : 1; /* End of Descriptor interrupt Enable;1-enable;0-mask */ unsigned int rd_perr_en : 1; /* Protocol Failure Interrupt Enable;1-enable;0-mask */ unsigned int rd_fail_en : 1; /* DMA Fail Interrupt Enable;1-enable;0-mask */ unsigned int rd_finish_en : 1; /* DMA Finish Event Interrupt Enable;1-enable;0-mask */ unsigned int rd_endian : 1; /* AHB Endian. 0-little endian; 1-big endian */ unsigned int rd_bus : 2; /* peripheral bus width;0x->8 bits,10->16 bits,11->32 bits */ unsigned int rd_burst_size : 2; /* DMA max burst size for every AHB request */ unsigned int rd_prot : 4; /* DMA protection control */ unsigned int : 1; unsigned int rd_chain_mode : 1; /* Descriptor Chain Mode;1-Descriptor Chain mode, 0-Direct DMA mode*/ unsigned int rd_continue : 1; /* Continue DMA operation */ unsigned int rd_start : 1; /* Start DMA transfer */#endif } bits;} GMAC_RXDMA_CTRL_T;typedef union{ unsigned int bits32; struct bit2_ff18 {#if (BIG_ENDIAN==1) unsigned int rd_first_des_ptr : 28;/* first descriptor address */ unsigned int rd_busy : 1;/* 1-RxDMA busy; 0-RxDMA idle */ unsigned int : 3;#else unsigned int : 3; unsigned int rd_busy : 1;/* 1-RxDMA busy; 0-RxDMA idle */ unsigned int rd_first_des_ptr : 28;/* first descriptor address */#endif } bits;} GMAC_RXDMA_FIRST_DESC_T;typedef union{ unsigned int bits32; struct bit2_ff1c {#if (BIG_ENDIAN==1) unsigned int ndar : 28; /* next descriptor address */ unsigned int eofie : 1; /* end of frame interrupt enable */ unsigned int : 1; unsigned int sof_eof : 2;#else unsigned int sof_eof : 2; unsigned int : 1; unsigned int eofie : 1; /* end of frame interrupt enable */ unsigned int ndar : 28; /* next descriptor address */#endif } bits;} GMAC_RXDMA_CURR_DESC_T;/********************************************//* Descriptor Format *//********************************************/typedef struct descriptor_t{ union frame_control_t { unsigned int bits32; struct bits_0000 {#if (BIG_ENDIAN==1) unsigned int own : 1; /* owner bit. 0-CPU, 1-DMA */ unsigned int derr : 1; /* data error during processing this descriptor */ unsigned int perr : 1; /* protocol error during processing this descriptor */ unsigned int csum_state : 3; /* checksum error status */ unsigned int vlan_tag : 1; /* 802.1q vlan tag packet */ unsigned int frame_state: 3; /* reference Rx Status1 */ unsigned int desc_count : 6; /* number of descriptors used for the current frame */ unsigned int buffer_size:16; /* transfer buffer size associated with current description*/#else unsigned int buffer_size:16; /* transfer buffer size associated with current description*/ unsigned int desc_count : 6; /* number of descriptors used for the current frame */ unsigned int frame_state: 3; /* reference Rx Status1 */ unsigned int vlan_tag : 1; /* 802.1q vlan tag packet */ unsigned int csum_state : 3; /* checksum error status */ unsigned int perr : 1; /* protocol error during processing this descriptor */ unsigned int derr : 1; /* data error during processing this descriptor */ unsigned int own : 1; /* owner bit. 0-CPU, 1-DMA */#endif } bits_rx; struct bits_0001 {#if (BIG_ENDIAN==1) unsigned int own : 1; /* owner bit. 0-CPU, 1-DMA */ unsigned int derr : 1; /* data error during processing this descriptor */ unsigned int perr : 1; /* protocol error during processing this descriptor */ unsigned int : 6; unsigned int success_tx : 1; /* successful transmitted */ unsigned int desc_count : 6; /* number of descriptors used for the current frame */ unsigned int buffer_size:16; /* transfer buffer size associated with current description*/#else unsigned int buffer_size:16; /* transfer buffer size associated with current description*/ unsigned int desc_count : 6; /* number of descriptors used for the current frame */ unsigned int success_tx : 1; /* successful transmitted */ unsigned int : 6; unsigned int perr : 1; /* protocol error during processing this descriptor */ unsigned int derr : 1; /* data error during processing this descriptor */ unsigned int own : 1; /* owner bit. 0-CPU, 1-DMA */#endif } bits_tx_in; struct bits_0002 {#if (BIG_ENDIAN==1) unsigned int own : 1; /* owner bit. 0-CPU, 1-DMA */ unsigned int derr : 1; /* data error during processing this descriptor */ unsigned int perr : 1; /* protocol error during processing this descriptor */ unsigned int : 2; unsigned int udp_csum_en: 1; /* TSS UDP checksum enable */ unsigned int tcp_csum_en: 1; /* TSS TCP checksum enable */ unsigned int ipv6_tx_en : 1; /* TSS IPv6 TX enable */ unsigned int ip_csum_en : 1; /* TSS IPv4 IP Header checksum enable */ unsigned int vlan_enable: 1; /* VLAN TIC insertion enable */ unsigned int desc_count : 6; /* number of descriptors used for the current frame */ unsigned int buffer_size:16; /* transfer buffer size associated with current description*/#else unsigned int buffer_size:16; /* transfer buffer size associated with current description*/ unsigned int desc_count : 6; /* number of descriptors used for the current frame */ unsigned int vlan_enable: 1; /* VLAN TIC insertion enable */ unsigned int ip_csum_en : 1; /* TSS IPv4 IP Header checksum enable */ unsigned int ipv6_tx_en : 1; /* TSS IPv6 TX enable */ unsigned int tcp_csum_en: 1; /* TSS TCP checksum enable */ unsigned int udp_csum_en: 1; /* TSS UDP checksum enable */ unsigned int : 2; unsigned int perr : 1; /* protocol error during processing this descriptor */ unsigned int derr : 1; /* data error during processing this descriptor */ unsigned int own : 1; /* owner bit. 0-CPU, 1-DMA */#endif } bits_tx_out; } frame_ctrl; union flag_status_t { unsigned int bits32; struct bits_0004 {#if (BIG_ENDIAN==1) unsigned int priority : 3; /* user priority extracted from receiving frame*/ unsigned int cfi : 1; /* cfi extracted from receiving frame*/ unsigned int vlan_id :12; /* VLAN ID extracted from receiving frame */ unsigned int frame_count:16; /* received frame byte count,include CRC,not include VLAN TIC */#else unsigned int frame_count:16; /* received frame byte count,include CRC,not include VLAN TIC */ unsigned int vlan_id :12; /* VLAN ID extracted from receiving frame */ unsigned int cfi : 1; /* cfi extracted from receiving frame*/ unsigned int priority : 3; /* user priority extracted from receiving frame*/#endif } bits_rx_status; struct bits_0005 {#if (BIG_ENDIAN==1) unsigned int priority : 3; /* user priority to transmit*/ unsigned int cfi : 1; /* cfi to transmit*/ unsigned int vlan_id :12; /* VLAN ID to transmit */ unsigned int frame_count:16; /* total tx frame byte count */#else unsigned int frame_count:16; /* total tx frame byte count */ unsigned int vlan_id :12; /* VLAN ID to transmit */ unsigned int cfi : 1; /* cfi to transmit*/ unsigned int priority : 3; /* user priority to transmit*/#endif } bits_tx_flag; } flag_status; unsigned int buf_adr; /* data buffer address */ union next_desc_t { unsigned int next_descriptor; struct bits_000c {#if (BIG_ENDIAN==1) unsigned int ndar :28; /* next descriptor address */ unsigned int eofie : 1; /* end of frame interrupt enable */ unsigned int : 1; unsigned int sof_eof : 2; /* 00-the linking descriptor 01-the last descriptor of a frame*/ /* 10-the first descriptor of a frame 11-only one descriptor for a frame*/#else unsigned int sof_eof : 2; /* 00-the linking descriptor 01-the last descriptor of a frame*/ /* 10-the first descriptor of a frame 11-only one descriptor for a frame*/ unsigned int : 1; unsigned int eofie : 1; /* end of frame interrupt enable */ unsigned int ndar :28; /* next descriptor address */#endif } bits; } next_desc;} GMAC_DESCRIPTOR_T;typedef struct gmac_conf { struct net_device *dev; int portmap; int vid; int flag; /* 1: active 0: non-active */} sys_gmac_conf; typedef struct gmac_private { unsigned char *tx_bufs; /* Tx bounce buffer region. */ unsigned char *rx_bufs; GMAC_DESCRIPTOR_T *tx_desc; /* point to virtual TX descriptor address*/ GMAC_DESCRIPTOR_T *rx_desc; /* point to virtual RX descriptor address*/ GMAC_DESCRIPTOR_T *tx_cur_desc; /* point to current TX descriptor */ GMAC_DESCRIPTOR_T *rx_cur_desc; /* point to current RX descriptor */ GMAC_DESCRIPTOR_T *tx_finished_desc; GMAC_DESCRIPTOR_T *rx_finished_desc; unsigned long cur_tx; unsigned int cur_rx; /* Index into the Rx buffer of next Rx pkt. */ unsigned int tx_flag; unsigned long dirty_tx; unsigned char *tx_buf[TX_DESC_NUM]; /* Tx bounce buffers */ dma_addr_t tx_desc_dma; /* physical TX descriptor address */ dma_addr_t rx_desc_dma; /* physical RX descriptor address */ dma_addr_t tx_bufs_dma; /* physical TX descriptor address */ dma_addr_t rx_bufs_dma; /* physical RX descriptor address */// struct net_device_stats stats;// spinlock_t lock;} GMAC_INFO_T;;struct reg_ioctl_data { unsigned int reg_addr; /* the register address */ unsigned int val_in; /* data write to the register */ unsigned int val_out; /* data read from the register */};#endif //_GMAC_SL2312_H⌨️ 快捷键说明
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