📄 sl_lepus_gmac.h
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* GMAC DMA Rx Description Word 1 Register * GMAC0 offset 0x8064 * GMAC1 offset 0xC064 **********************************************************************/typedef union{ unsigned int bits32; struct rxdesc_word1 {#if (BIG_ENDIAN==1) unsigned int sw_id : 16; // bit 31:16 Software ID unsigned int byte_count : 16; // bit 15: 0 Rx Frame Byte Count#else unsigned int byte_count : 16; // bit 15: 0 Rx Frame Byte Count unsigned int sw_id : 16; // bit 31:16 Software ID#endif } bits;} GMAC_RXDESC_1_T;/********************************************************************** * GMAC DMA Rx Description Word 2 Register * GMAC0 offset 0x8068 * GMAC1 offset 0xC068 **********************************************************************/typedef union{ unsigned int bits32; unsigned int buf_adr;} GMAC_RXDESC_2_T;#define RX_INSERT_NONE 0#define RX_INSERT_1_BYTE 1#define RX_INSERT_2_BYTE 2#define RX_INSERT_3_BYTE 3/********************************************************************** * GMAC DMA Rx Description Word 3 Register * GMAC0 offset 0x806C * GMAC1 offset 0xC06C **********************************************************************/typedef union{ unsigned int bits32; struct rxdesc_word3 {#if (BIG_ENDIAN==1) unsigned int sof_eof : 2; // bit 31:30 11: only one, 10: first, 01: last, 00: linking unsigned int eofie : 1; // bit 29 End of frame interrupt enable unsigned int ctrl_flag : 1; // bit 28 Control Flag is present unsigned int out_of_seq : 1; // bit 27 Out of Sequence packet unsigned int option : 1; // bit 26 IPV4 option or IPV6 extension header unsigned int abnormal : 1; // bit 25 abnormal case found unsigned int dup_ack : 1; // bit 24 Duplicated ACK detected unsigned int l7_offset : 8; // bit 23: 16 L7 data offset unsigned int l4_offset : 8; // bit 15: 8 L4 data offset unsigned int l3_offset : 8; // bit 7: 0 L3 data offset#else unsigned int l3_offset : 8; // bit 7: 0 L3 data offset unsigned int l4_offset : 8; // bit 15: 8 L4 data offset unsigned int l7_offset : 8; // bit 23: 16 L7 data offset unsigned int dup_ack : 1; // bit 24 Duplicated ACK detected unsigned int abnormal : 1; // bit 25 abnormal case found unsigned int option : 1; // bit 26 IPV4 option or IPV6 extension header unsigned int out_of_seq : 1; // bit 27 Out of Sequence packet unsigned int ctrl_flag : 1; // bit 28 Control Flag is present unsigned int eofie : 1; // bit 29 End of frame interrupt enable unsigned int sof_eof : 2; // bit 31:30 11: only one, 10: first, 01: last, 00: linking#endif } bits;} GMAC_RXDESC_3_T;#define RX_DESC_SOF_BIT 2#define RX_DESC_EOF_BIT 1/********************************************************************** * GMAC Rx Descriptor **********************************************************************/typedef struct{ GMAC_RXDESC_0_T word0; GMAC_RXDESC_1_T word1; GMAC_RXDESC_2_T word2; GMAC_RXDESC_3_T word3;} GMAC_RXDESC_T;/********************************************************************** * GMAC Hash Engine Enable/Action Register 0 Offset Register * GMAC0 offset 0x8070 * GMAC1 offset 0xC070 **********************************************************************/typedef union{ unsigned int bits32; struct bit_8070 {#if (BIG_ENDIAN==1) unsigned int mr1en : 1; // bit 31 Enable Matching Rule 1 unsigned int reserved1 : 4; // bit 30:27 unsigned int mr1_action : 5; // bit 26:22 Matching Rule 1 action offset unsigned int mr1hel : 6; // bit 21:16 match rule 1 hash entry size unsigned int mr0en : 1; // bit 15 Enable Matching Rule 0 unsigned int reserved0 : 4; // bit 14:11 unsigned int mr0_action : 5; // bit 10:6 Matching Rule 0 action offset unsigned int mr0hel : 6; // bit 5:0 match rule 0 hash entry size#else unsigned int mr0hel : 6; // bit 5:0 match rule 0 hash entry size unsigned int mr0_action : 5; // bit 10:6 Matching Rule 0 action offset unsigned int reserved0 : 4; // bit 14:11 unsigned int mr0en : 1; // bit 15 Enable Matching Rule 0 unsigned int mr1hel : 6; // bit 21:16 match rule 1 hash entry size unsigned int mr1_action : 5; // bit 26:22 Matching Rule 1 action offset unsigned int reserved1 : 4; // bit 30:27 unsigned int mr1en : 1; // bit 31 Enable Matching Rule 1#endif } bits;} GMAC_HASH_ENABLE_REG0_T; /********************************************************************** * GMAC Hash Engine Enable/Action Register 1 Offset Register * GMAC0 offset 0x8074 * GMAC1 offset 0xC074 **********************************************************************/typedef union{ unsigned int bits32; struct bit_8074 {#if (BIG_ENDIAN==1) unsigned int mr3en : 1; // bit 31 Enable Matching Rule 3 unsigned int reserved3 : 4; // bit 30:27 unsigned int mr3_action : 5; // bit 26:22 Matching Rule 3 action offset unsigned int mr3hel : 6; // bit 21:16 match rule 3 hash entry size unsigned int mr2en : 1; // bit 15 Enable Matching Rule 2 unsigned int reserved2 : 4; // bit 14:11 unsigned int mr2_action : 5; // bit 10:6 Matching Rule 2 action offset unsigned int mr2hel : 6; // bit 5:0 match rule 2 hash entry size#else unsigned int mr2hel : 6; // bit 5:0 match rule 2 hash entry size unsigned int mr2_action : 5; // bit 10:6 Matching Rule 2 action offset unsigned int reserved2 : 4; // bit 14:11 unsigned int mr2en : 1; // bit 15 Enable Matching Rule 2 unsigned int mr3hel : 6; // bit 21:16 match rule 3 hash entry size unsigned int mr3_action : 5; // bit 26:22 Matching Rule 3 action offset unsigned int reserved1 : 4; // bit 30:27 unsigned int mr3en : 1; // bit 31 Enable Matching Rule 3#endif } bits;} GMAC_HASH_ENABLE_REG1_T; /********************************************************************** * GMAC Matching Rule Control Register 0 * GMAC0 offset 0x8078 * GMAC1 offset 0xC078 **********************************************************************/typedef union{ unsigned int bits32; struct bit_8078 {#if (BIG_ENDIAN==1) unsigned int l2 : 1; // bit 31 L2 matching enable unsigned int l3 : 1; // bit 30 L3 matching enable unsigned int l4 : 1; // bit 29 L4 matching enable unsigned int l7 : 1; // bit 28 L7 matching enable unsigned int port : 1; // bit 27 PORT ID matching enable unsigned int priority : 3; // bit 26:24 priority if multi-rules matched unsigned int da : 1; // bit 23 MAC DA enable unsigned int sa : 1; // bit 22 MAC SA enable unsigned int ether_type : 1; // bit 21 Ethernet type enable unsigned int vlan : 1; // bit 20 VLAN ID enable unsigned int pppoe : 1; // bit 19 PPPoE Session ID enable unsigned int reserved1 : 3; // bit 18:16 unsigned int ip_version : 1; // bit 15 0: IPV4, 1: IPV6 unsigned int ip_hdr_len : 1; // bit 14 IPV4 Header length unsigned int flow_lable : 1; // bit 13 IPV6 Flow label unsigned int tos_traffic : 1; // bit 12 IPV4 TOS or IPV6 Traffice Class unsigned int reserved2 : 4; // bit 11:8 unsigned int sprx : 8; // bit 7:0 Support Protocol Register 7:0#else unsigned int sprx : 8; // bit 7:0 Support Protocol Register 7:0 unsigned int reserved2 : 4; // bit 11:8 unsigned int tos_traffic : 1; // bit 12 IPV4 TOS or IPV6 Traffice Class unsigned int flow_lable : 1; // bit 13 IPV6 Flow label unsigned int ip_hdr_len : 1; // bit 14 IPV4 Header length unsigned int ip_version : 1; // bit 15 0: IPV4, 1: IPV6 unsigned int reserved1 : 3; // bit 18:16 unsigned int pppoe : 1; // bit 19 PPPoE Session ID enable unsigned int vlan : 1; // bit 20 VLAN ID enable unsigned int ether_type : 1; // bit 21 Ethernet type enable unsigned int sa : 1; // bit 22 MAC SA enable unsigned int da : 1; // bit 23 MAC DA enable unsigned int priority : 3; // bit 26:24 priority if multi-rules matched unsigned int port : 1; // bit 27 PORT ID matching enable unsigned int l7 : 1; // bit 28 L7 matching enable unsigned int l4 : 1; // bit 29 L4 matching enable unsigned int l3 : 1; // bit 30 L3 matching enable unsigned int l2 : 1; // bit 31 L2 matching enable#endif } bits;} GMAC_MRxCR0_T;#define MR_L2_BIT BIT(31)#define MR_L3_BIT BIT(30)#define MR_L4_BIT BIT(29)#define MR_L7_BIT BIT(28)#define MR_PORT_BIT BIT(27)#define MR_PRIORITY_BIT BIT(26)#define MR_DA_BIT BIT(23)#define MR_SA_BIT BIT(22)#define MR_ETHER_TYPE_BIT BIT(21)#define MR_VLAN_BIT BIT(20)#define MR_PPPOE_BIT BIT(19)#define MR_IP_VER_BIT BIT(15)#define MR_IP_HDR_LEN_BIT BIT(14)#define MR_FLOW_LABLE_BIT BIT(13)#define MR_TOS_TRAFFIC_BIT BIT(12)#define MR_SPR_BIT(x) BIT(x)#define MR_SPR_BITS 0xff/********************************************************************** * GMAC Matching Rule Control Register 1 * GMAC0 offset 0x807C * GMAC1 offset 0xC07C **********************************************************************/ typedef union{ unsigned int bits32; struct bit_807C {#if (BIG_ENDIAN==1) unsigned int sip : 1; // bit 31 Srce IP unsigned int sip_netmask : 7; // bit 30:24 Srce IP net mask, number of mask bits unsigned int dip : 1; // bit 23 Dest IP unsigned int dip_netmask : 7; // bit 22:16 Dest IP net mask, number of mask bits unsigned int l4_byte0_15 : 16; // bit 15: 0 #else unsigned int l4_byte0_15 : 16; // bit 15: 0 unsigned int dip_netmask : 7; // bit 22:16 Dest IP net mask, number of mask bits unsigned int dip : 1; // bit 23 Dest IP unsigned int sip_netmask : 7; // bit 30:24 Srce IP net mask, number of mask bits unsigned int sip : 1; // bit 31 Srce IP#endif } bits;} GMAC_MRxCR1_T;/********************************************************************** * GMAC Matching Rule Control Register 2 * GMAC0 offset 0x8080 * GMAC1 offset 0xC080 **********************************************************************/ typedef union{ unsigned int bits32; struct bit_8080 {#if (BIG_ENDIAN==1) unsigned int l4_byte16_24: 8; // bit 31: 24 unsigned int l7_byte0_23 : 24; // bit 23:0 #else unsigned int l7_byte0_23 : 24; // bit 23:0 unsigned int l4_byte16_24: 8; // bit 31: 24 #endif } bits;} GMAC_MRxCR2_T; /********************************************************************** * GMAC Support registers * GMAC0 offset 0x80A8 * GMAC1 offset 0xC0A8 **********************************************************************/ typedef union{ unsigned int bits32; struct bit_80A8 {#if (BIG_ENDIAN==1) unsigned int reserved: 21; // bit 31:11 unsigned int swap : 3; // bit 10:8 Swap unsigned int protocol: 8; // bit 7:0 Supported protocol #else unsigned int protocol: 8; // bit 7:0 Supported protocol unsigned int swap : 3; // bit 10:8 Swap unsigned int reserved: 21; // bit 31:11 #endif } bits;} GMAC_SPR_T;/********************************************************************** * GMAC_AHB_WEIGHT registers * GMAC0 offset 0x80C8 * GMAC1 offset 0xC0C8 **********************************************************************/ typedef union{ unsigned int bits32; struct bit_80C8 {#if (BIG_ENDIAN==1) unsigned int reserved : 7; // 31:25 unsigned int tqDV_threshold : 5; // 24:20 DMA TqCtrl to Start tqDV FIFO Threshold unsigned int pre_req : 5; // 19:15 Rx Data Pre Request FIFO Threshold unsigned int tx_wei⌨️ 快捷键说明
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