sl_lepus_gmac.h

某个ARM9板子的实际bootloader 对裁剪

	{
#if (BIG_ENDIAN==1)
		unsigned int    reserved		: 8;	// bit 31:24
		unsigned int    hw_tq3			: 6;	// bit 23:18	HW TX Queue 0
		unsigned int    hw_tq2			: 6;	// bit 17:12	HW TX Queue 1
		unsigned int    hw_tq1			: 6;	// bit 11:6		HW TX Queue 2
		unsigned int    hw_tq0			: 6;	// bit 5:0		HW TX Queue 3
#else
		unsigned int    hw_tq0			: 6;	// bit 5:0		HW TX Queue 3
		unsigned int    hw_tq1			: 6;	// bit 11:6		HW TX Queue 2
		unsigned int    hw_tq2			: 6;	// bit 17:12	HW TX Queue 1
		unsigned int    hw_tq3			: 6;	// bit 23:18	HW TX Queue 0
		unsigned int    reserved		: 8;	// bit 31:24
#endif
	} bits;
} GMAC_TX_WCR0_T;	// Weighting Control Register 0

/**********************************************************************
 * GMAC Tx Weighting Control Register 1	
 * GMAC0 offset 0x8008
 * GMAC1 offset 0xC008
 **********************************************************************/
typedef union
{
	unsigned int bits32;
	struct bit_8008 
	{
#if (BIG_ENDIAN==1)
		unsigned int    reserved		: 2;	// bit 31:30
		unsigned int    sw_tq5			: 5;	// bit 29:25	SW TX Queue 5
		unsigned int    sw_tq4			: 5;	// bit 24:20	SW TX Queue 4
		unsigned int    sw_tq3			: 5;	// bit 19:15	SW TX Queue 3
		unsigned int    sw_tq2			: 5;	// bit 14:10	SW TX Queue 2
		unsigned int    sw_tq1			: 5;	// bit 9:5		SW TX Queue 1
		unsigned int    sw_tq0			: 5;	// bit 4:0		SW TX Queue 0
#else
		unsigned int    sw_tq0			: 5;	// bit 4:0		SW TX Queue 0
		unsigned int    sw_tq1			: 5;	// bit 9:5		SW TX Queue 1
		unsigned int    sw_tq2			: 5;	// bit 14:10	SW TX Queue 2
		unsigned int    sw_tq3			: 5;	// bit 19:15	SW TX Queue 3
		unsigned int    sw_tq4			: 5;	// bit 24:20	SW TX Queue 4
		unsigned int    sw_tq5			: 5;	// bit 29:25	SW TX Queue 5
		unsigned int    reserved		: 2;	// bit 31:30
#endif
	} bits;
} GMAC_TX_WCR1_T;	// Weighting Control Register 1

/**********************************************************************
 * Queue Read/Write Pointer
 * GMAC SW TX Queue 0~5 Read/Write Pointer register
 * GMAC0 offset 0x800C ~ 0x8020
 * GMAC1 offset 0xC00C ~ 0xC020
 * GMAC HW TX Queue 0~3 Read/Write Pointer register
 * GMAC0 offset 0x8024 ~ 0x8030
 * GMAC1 offset 0xC024 ~ 0xC030
 **********************************************************************/
// see DMA_RWPTR_T structure

/**********************************************************************
 * GMAC DMA Tx First Description Address Register
 * GMAC0 offset 0x8038
 * GMAC1 offset 0xC038
 **********************************************************************/
typedef union
{
	unsigned int bits32;
	struct bit_8038
	{
#if (BIG_ENDIAN==1)
		unsigned int td_first_des_ptr	: 28;	// bit 31:4	first descriptor address 
		unsigned int td_busy			:  1;	// bit 3	1: TxDMA busy; 0: TxDMA idle
		unsigned int reserved			:  3;
#else
		unsigned int reserved			:  3;
		unsigned int td_busy			:  1;	// bit 3	1: TxDMA busy; 0: TxDMA idle
		unsigned int td_first_des_ptr	: 28;	// bit 31:4	first descriptor address 
#endif
	} bits;
} GMAC_TXDMA_FIRST_DESC_T;

/**********************************************************************
 * GMAC DMA Tx Current Description Address Register
 * GMAC0 offset 0x803C
 * GMAC1 offset 0xC03C
 **********************************************************************/
typedef union
{
	unsigned int bits32;
	struct bit_803C
	{
#if (BIG_ENDIAN==1)
		unsigned int td_curr_desc_ptr	: 28;	// bit 31:4	current descriptor address 
		unsigned int reserved			:  4;
#else
		unsigned int reserved			:  4;
		unsigned int td_curr_desc_ptr	: 28;	// bit 31:4	current descriptor address 
#endif
	} bits;
} GMAC_TXDMA_CURR_DESC_T;

/**********************************************************************
 * GMAC DMA Tx Description Word 0 Register
 * GMAC0 offset 0x8040
 * GMAC1 offset 0xC040
 **********************************************************************/
typedef union
{
	unsigned int bits32;
	struct bit_8040
	{
#if (BIG_ENDIAN==1)
		unsigned int reserved		: 1;	// bit 31
		unsigned int derr			: 1;	// bit 30	 data error during processing this descriptor
		unsigned int perr			: 1;	// bit 29	 protocol error during processing this descriptor
		unsigned int status_rvd		: 6;	// bit 28:23 Tx Status, Reserved bits
		unsigned int status_tx_ok	: 1;	// bit 22    Tx Status, 1: Successful 0: Failed
		unsigned int desc_count 	: 6;	// bit 21:16 number of descriptors used for the current frame
		unsigned int buffer_size 	: 16;	// bit 15:0  Transfer size
#else
		unsigned int buffer_size 	: 16;	// bit 15:0  Transfer size
		unsigned int desc_count 	: 6;	// bit 21:16 number of descriptors used for the current frame
		unsigned int status_tx_ok	: 1;	// bit 22    Tx Status, 1: Successful 0: Failed
		unsigned int status_rvd		: 6;	// bit 28:23 Tx Status, Reserved bits
		unsigned int perr			: 1;	// bit 29	 protocol error during processing this descriptor
		unsigned int derr			: 1;	// bit 30	 data error during processing this descriptor
		unsigned int reserved		: 1;	// bit 31
#endif
	} bits;
} GMAC_TXDESC_0_T;

/**********************************************************************
 * GMAC DMA Tx Description Word 1 Register
 * GMAC0 offset 0x8044
 * GMAC1 offset 0xC044
 **********************************************************************/
typedef union
{
	unsigned int bits32;
	struct txdesc_word1
	{
#if (BIG_ENDIAN==1)
		unsigned int	reserved	: 9;	// bit 31:19 	Tx Flag, Reserved
		unsigned int	ip_fixed_len: 1;	// bit 22
		unsigned int	bypass_tss	: 1;	// bit 21
		unsigned int	udp_chksum	: 1;	// bit 20		UDP Checksum Enable
		unsigned int	tcp_chksum	: 1;	// bit 19		TCP Checksum Enable
		unsigned int	ipv6_enable	: 1;	// bit 18		IPV6 Tx Enable
		unsigned int	ip_chksum	: 1;	// bit 17		IPV4 Header Checksum Enable
		unsigned int	mtu_enable	: 1;	// bit 16		TSS segmentation use MTU setting
		unsigned int	byte_count	: 16;	// bit 15: 0	Tx Frame Byte Count
#else
		unsigned int	byte_count	: 16;	// bit 15: 0	Tx Frame Byte Count
		unsigned int	mtu_enable	: 1;	// bit 16		TSS segmentation use MTU setting
		unsigned int	ip_chksum	: 1;	// bit 17		IPV4 Header Checksum Enable
		unsigned int	ipv6_enable	: 1;	// bit 18		IPV6 Tx Enable
		unsigned int	tcp_chksum	: 1;	// bit 19		TCP Checksum Enable
		unsigned int	udp_chksum	: 1;	// bit 20		UDP Checksum Enable
		unsigned int	bypass_tss	: 1;	// bit 21
		unsigned int	ip_fixed_len: 1;	// bit 22
		unsigned int	reserved	: 9;	// bit 31:19 	Tx Flag, Reserved
#endif
	} bits;
} GMAC_TXDESC_1_T;

/**********************************************************************
 * GMAC DMA Tx Description Word 2 Register
 * GMAC0 offset 0x8048
 * GMAC1 offset 0xC048
 **********************************************************************/
typedef union
{
	unsigned int	bits32;
	unsigned int 	buf_adr;
} GMAC_TXDESC_2_T;

/**********************************************************************
 * GMAC DMA Tx Description Word 3 Register
 * GMAC0 offset 0x804C
 * GMAC1 offset 0xC04C
 **********************************************************************/
typedef union
{
	unsigned int bits32;
	struct txdesc_word3
	{
#if (BIG_ENDIAN==1)
		unsigned int	sof_eof		: 2;	// bit 31:30 	11: only one, 10: first, 01: last, 00: linking
		unsigned int	eofie		: 1;	// bit 29		End of frame interrupt enable
		unsigned int	reserved	: 18;	// bit 28:11
		unsigned int	mtu_size	: 11;	// bit 10: 0	Tx Frame Byte Count
#else
		unsigned int	mtu_size	: 11;	// bit 10: 0	Tx Frame Byte Count
		unsigned int	reserved	: 18;	// bit 28:11
		unsigned int	eofie		: 1;	// bit 29		End of frame interrupt enable
		unsigned int	sof_eof		: 2;	// bit 31:30 	11: only one, 10: first, 01: last, 00: linking
#endif
	} bits;
} GMAC_TXDESC_3_T;

#define TX_DESC_SOF_BIT			2
#define TX_DESC_EOF_BIT			1

/**********************************************************************
 * GMAC Tx Descriptor
 **********************************************************************/
typedef struct
{
	GMAC_TXDESC_0_T	word0;
	GMAC_TXDESC_1_T	word1;
	GMAC_TXDESC_2_T	word2;
	GMAC_TXDESC_3_T	word3;
} GMAC_TXDESC_T;


/**********************************************************************
 * GMAC DMA Rx First Description Address Register
 * GMAC0 offset 0x8058
 * GMAC1 offset 0xC058
 **********************************************************************/
typedef union
{
	unsigned int bits32;
	struct bit_8058
	{
#if (BIG_ENDIAN==1)
		unsigned int rd_first_des_ptr	: 28;	// bit 31:4 first descriptor address
		unsigned int rd_busy			:  1;	// bit 3	1-RxDMA busy; 0-RxDMA idle
		unsigned int reserved			:  3;	// bit 2:0
#else
		unsigned int reserved			:  3;	// bit 2:0
		unsigned int rd_busy			:  1;	// bit 3	1-RxDMA busy; 0-RxDMA idle
		unsigned int rd_first_des_ptr	: 28;	// bit 31:4 first descriptor address
#endif
	} bits;
} GMAC_RXDMA_FIRST_DESC_T;

/**********************************************************************
 * GMAC DMA Rx Current Description Address Register
 * GMAC0 offset 0x805C
 * GMAC1 offset 0xC05C
 **********************************************************************/
typedef union
{
	unsigned int bits32;
	struct bit_805C
	{
#if (BIG_ENDIAN==1)
		unsigned int rd_curr_des_ptr	: 28;	// bit 31:4 current descriptor address
		unsigned int reserved			:  4;	// bit 3:0
#else
		unsigned int reserved			:  4;	// bit 3:0
		unsigned int rd_curr_des_ptr	: 28;	// bit 31:4 current descriptor address
#endif
	} bits;
} GMAC_RXDMA_CURR_DESC_T;

/**********************************************************************
 * GMAC DMA Rx Description Word 0 Register
 * GMAC0 offset 0x8060
 * GMAC1 offset 0xC060
 **********************************************************************/
typedef union
{
	unsigned int bits32;
	struct bit_8060
	{
#if (BIG_ENDIAN==1)
		unsigned int drop			: 1;	// bit 31	 TOE/CIS Queue Full dropped packet to default queue
		unsigned int derr			: 1;	// bit 30	 data error during processing this descriptor
		unsigned int perr			: 1;	// bit 29	 protocol error during processing this descriptor
		unsigned int chksum_status	: 3;	// bit 28:26 Check Sum Status
		unsigned int status			: 4;	// bit 24:22 Status of rx frame
		unsigned int desc_count 	: 6;	// bit 21:16 number of descriptors used for the current frame
		unsigned int buffer_size 	: 16;	// bit 15:0  number of descriptors used for the current frame
#else
		unsigned int buffer_size 	: 16;	// bit 15:0  number of descriptors used for the current frame
		unsigned int desc_count 	: 6;	// bit 21:16 number of descriptors used for the current frame
		unsigned int status			: 4;	// bit 24:22 Status of rx frame
		unsigned int chksum_status	: 3;	// bit 28:26 Check Sum Status
		unsigned int perr			: 1;	// bit 29	 protocol error during processing this descriptor
		unsigned int derr			: 1;	// bit 30	 data error during processing this descriptor
		unsigned int drop			: 1;	// bit 31	 TOE/CIS Queue Full dropped packet to default queue
#endif
	} bits;
} GMAC_RXDESC_0_T;

#define	RX_CHKSUM_IP_UDP_TCP_OK			0
#define	RX_CHKSUM_IP_OK_ONLY			1
#define	RX_CHKSUM_NONE					2
#define	RX_CHKSUM_IP_ERR_UNKNOWN		4
#define	RX_CHKSUM_IP_ERR				5
#define	RX_CHKSUM_TCP_UDP_ERR			6
#define RX_CHKSUM_NUM					8

#define RX_STATUS_GOOD_FRAME			0
#define RX_STATUS_TOO_LONG_GOOD_CRC		1
#define RX_STATUS_RUNT_FRAME			2
#define RX_STATUS_SFD_NOT_FOUND			3
#define RX_STATUS_CRC_ERROR				4
#define RX_STATUS_TOO_LONG_BAD_CRC		5
#define RX_STATUS_ALIGNMENT_ERROR		6
#define RX_STATUS_TOO_LONG_BAD_ALIGN	7
#define RX_STATUS_RX_ERR				8
#define RX_STATUS_DA_FILTERED			9
#define RX_STATUS_BUFFER_FULL			10
#define RX_STATUS_NUM					16

/**********************************************************************