📄 sl_lepus_gmac.h
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/********************************************************************** * Interrupt Status Register 2 (offset 0x0040) * Interrupt Mask Register 2 (offset 0x0044) * Interrupt Select Register 2 (offset 0x0048) **********************************************************************/typedef union{ unsigned int bits32; struct bit_0040 {#if (BIG_ENDIAN==1) unsigned int toe_q31_full : 1; // bit 31 TOE Queue 31 Full Interrupt unsigned int toe_q30_full : 1; // bit 30 TOE Queue 30 Full Interrupt unsigned int toe_q29_full : 1; // bit 29 TOE Queue 29 Full Interrupt unsigned int toe_q28_full : 1; // bit 28 TOE Queue 28 Full Interrupt unsigned int toe_q27_full : 1; // bit 27 TOE Queue 27 Full Interrupt unsigned int toe_q26_full : 1; // bit 26 TOE Queue 26 Full Interrupt unsigned int toe_q25_full : 1; // bit 25 TOE Queue 25 Full Interrupt unsigned int toe_q24_full : 1; // bit 24 TOE Queue 24 Full Interrupt unsigned int toe_q23_full : 1; // bit 23 TOE Queue 23 Full Interrupt unsigned int toe_q22_full : 1; // bit 22 TOE Queue 22 Full Interrupt unsigned int toe_q21_full : 1; // bit 21 TOE Queue 21 Full Interrupt unsigned int toe_q20_full : 1; // bit 20 TOE Queue 20 Full Interrupt unsigned int toe_q19_full : 1; // bit 19 TOE Queue 19 Full Interrupt unsigned int toe_q18_full : 1; // bit 18 TOE Queue 18 Full Interrupt unsigned int toe_q17_full : 1; // bit 17 TOE Queue 17 Full Interrupt unsigned int toe_q16_full : 1; // bit 16 TOE Queue 16 Full Interrupt unsigned int toe_q15_full : 1; // bit 15 TOE Queue 15 Full Interrupt unsigned int toe_q14_full : 1; // bit 14 TOE Queue 14 Full Interrupt unsigned int toe_q13_full : 1; // bit 13 TOE Queue 13 Full Interrupt unsigned int toe_q12_full : 1; // bit 12 TOE Queue 12 Full Interrupt unsigned int toe_q11_full : 1; // bit 11 TOE Queue 11 Full Interrupt unsigned int toe_q10_full : 1; // bit 10 TOE Queue 10 Full Interrupt unsigned int toe_q9_full : 1; // bit 9 TOE Queue 9 Full Interrupt unsigned int toe_q8_full : 1; // bit 8 TOE Queue 8 Full Interrupt unsigned int toe_q7_full : 1; // bit 7 TOE Queue 7 Full Interrupt unsigned int toe_q6_full : 1; // bit 6 TOE Queue 6 Full Interrupt unsigned int toe_q5_full : 1; // bit 5 TOE Queue 5 Full Interrupt unsigned int toe_q4_full : 1; // bit 4 TOE Queue 4 Full Interrupt unsigned int toe_q3_full : 1; // bit 3 TOE Queue 3 Full Interrupt unsigned int toe_q2_full : 1; // bit 2 TOE Queue 2 Full Interrupt unsigned int toe_q1_full : 1; // bit 1 TOE Queue 1 Full Interrupt unsigned int toe_q0_full : 1; // bit 0 TOE Queue 0 Full Interrupt#else unsigned int toe_q0_full : 1; // bit 0 TOE Queue 0 Full Interrupt unsigned int toe_q1_full : 1; // bit 1 TOE Queue 1 Full Interrupt unsigned int toe_q2_full : 1; // bit 2 TOE Queue 2 Full Interrupt unsigned int toe_q3_full : 1; // bit 3 TOE Queue 3 Full Interrupt unsigned int toe_q4_full : 1; // bit 4 TOE Queue 4 Full Interrupt unsigned int toe_q5_full : 1; // bit 5 TOE Queue 5 Full Interrupt unsigned int toe_q6_full : 1; // bit 6 TOE Queue 6 Full Interrupt unsigned int toe_q7_full : 1; // bit 7 TOE Queue 7 Full Interrupt unsigned int toe_q8_full : 1; // bit 8 TOE Queue 8 Full Interrupt unsigned int toe_q9_full : 1; // bit 9 TOE Queue 9 Full Interrupt unsigned int toe_q10_full : 1; // bit 10 TOE Queue 10 Full Interrupt unsigned int toe_q11_full : 1; // bit 11 TOE Queue 11 Full Interrupt unsigned int toe_q12_full : 1; // bit 12 TOE Queue 12 Full Interrupt unsigned int toe_q13_full : 1; // bit 13 TOE Queue 13 Full Interrupt unsigned int toe_q14_full : 1; // bit 14 TOE Queue 14 Full Interrupt unsigned int toe_q15_full : 1; // bit 15 TOE Queue 15 Full Interrupt unsigned int toe_q16_full : 1; // bit 16 TOE Queue 16 Full Interrupt unsigned int toe_q17_full : 1; // bit 17 TOE Queue 17 Full Interrupt unsigned int toe_q18_full : 1; // bit 18 TOE Queue 18 Full Interrupt unsigned int toe_q19_full : 1; // bit 19 TOE Queue 19 Full Interrupt unsigned int toe_q20_full : 1; // bit 20 TOE Queue 20 Full Interrupt unsigned int toe_q21_full : 1; // bit 21 TOE Queue 21 Full Interrupt unsigned int toe_q22_full : 1; // bit 22 TOE Queue 22 Full Interrupt unsigned int toe_q23_full : 1; // bit 23 TOE Queue 23 Full Interrupt unsigned int toe_q24_full : 1; // bit 24 TOE Queue 24 Full Interrupt unsigned int toe_q25_full : 1; // bit 25 TOE Queue 25 Full Interrupt unsigned int toe_q26_full : 1; // bit 26 TOE Queue 26 Full Interrupt unsigned int toe_q27_full : 1; // bit 27 TOE Queue 27 Full Interrupt unsigned int toe_q28_full : 1; // bit 28 TOE Queue 28 Full Interrupt unsigned int toe_q29_full : 1; // bit 29 TOE Queue 29 Full Interrupt unsigned int toe_q30_full : 1; // bit 30 TOE Queue 30 Full Interrupt unsigned int toe_q31_full : 1; // bit 31 TOE Queue 31 Full Interrupt#endif } bits;} INTR_REG2_T;#define TOE_QL_FULL_INT_BIT(x) BIT(x)/********************************************************************** * Interrupt Status Register 3 (offset 0x0050) * Interrupt Mask Register 3 (offset 0x0054) * Interrupt Select Register 3 (offset 0x0058) **********************************************************************/typedef union{ unsigned int bits32; struct bit_0050 {#if (BIG_ENDIAN==1) unsigned int toe_q63_full : 1; // bit 63 TOE Queue 63 Full Interrupt unsigned int toe_q62_full : 1; // bit 62 TOE Queue 62 Full Interrupt unsigned int toe_q61_full : 1; // bit 61 TOE Queue 61 Full Interrupt unsigned int toe_q60_full : 1; // bit 60 TOE Queue 60 Full Interrupt unsigned int toe_q59_full : 1; // bit 59 TOE Queue 59 Full Interrupt unsigned int toe_q58_full : 1; // bit 58 TOE Queue 58 Full Interrupt unsigned int toe_q57_full : 1; // bit 57 TOE Queue 57 Full Interrupt unsigned int toe_q56_full : 1; // bit 56 TOE Queue 56 Full Interrupt unsigned int toe_q55_full : 1; // bit 55 TOE Queue 55 Full Interrupt unsigned int toe_q54_full : 1; // bit 54 TOE Queue 54 Full Interrupt unsigned int toe_q53_full : 1; // bit 53 TOE Queue 53 Full Interrupt unsigned int toe_q52_full : 1; // bit 52 TOE Queue 52 Full Interrupt unsigned int toe_q51_full : 1; // bit 51 TOE Queue 51 Full Interrupt unsigned int toe_q50_full : 1; // bit 50 TOE Queue 50 Full Interrupt unsigned int toe_q49_full : 1; // bit 49 TOE Queue 49 Full Interrupt unsigned int toe_q48_full : 1; // bit 48 TOE Queue 48 Full Interrupt unsigned int toe_q47_full : 1; // bit 47 TOE Queue 47 Full Interrupt unsigned int toe_q46_full : 1; // bit 46 TOE Queue 46 Full Interrupt unsigned int toe_q45_full : 1; // bit 45 TOE Queue 45 Full Interrupt unsigned int toe_q44_full : 1; // bit 44 TOE Queue 44 Full Interrupt unsigned int toe_q43_full : 1; // bit 43 TOE Queue 43 Full Interrupt unsigned int toe_q42_full : 1; // bit 42 TOE Queue 42 Full Interrupt unsigned int toe_q41_full : 1; // bit 41 TOE Queue 41 Full Interrupt unsigned int toe_q40_full : 1; // bit 40 TOE Queue 40 Full Interrupt unsigned int toe_q39_full : 1; // bit 39 TOE Queue 39 Full Interrupt unsigned int toe_q38_full : 1; // bit 38 TOE Queue 38 Full Interrupt unsigned int toe_q37_full : 1; // bit 37 TOE Queue 37 Full Interrupt unsigned int toe_q36_full : 1; // bit 36 TOE Queue 36 Full Interrupt unsigned int toe_q35_full : 1; // bit 35 TOE Queue 35 Full Interrupt unsigned int toe_q34_full : 1; // bit 34 TOE Queue 34 Full Interrupt unsigned int toe_q33_full : 1; // bit 33 TOE Queue 33 Full Interrupt unsigned int toe_q32_full : 1; // bit 32 TOE Queue 32 Full Interrupt#else unsigned int toe_q32_full : 1; // bit 32 TOE Queue 32 Full Interrupt unsigned int toe_q33_full : 1; // bit 33 TOE Queue 33 Full Interrupt unsigned int toe_q34_full : 1; // bit 34 TOE Queue 34 Full Interrupt unsigned int toe_q35_full : 1; // bit 35 TOE Queue 35 Full Interrupt unsigned int toe_q36_full : 1; // bit 36 TOE Queue 36 Full Interrupt unsigned int toe_q37_full : 1; // bit 37 TOE Queue 37 Full Interrupt unsigned int toe_q38_full : 1; // bit 38 TOE Queue 38 Full Interrupt unsigned int toe_q39_full : 1; // bit 39 TOE Queue 39 Full Interrupt unsigned int toe_q40_full : 1; // bit 40 TOE Queue 40 Full Interrupt unsigned int toe_q41_full : 1; // bit 41 TOE Queue 41 Full Interrupt unsigned int toe_q42_full : 1; // bit 42 TOE Queue 42 Full Interrupt unsigned int toe_q43_full : 1; // bit 43 TOE Queue 43 Full Interrupt unsigned int toe_q44_full : 1; // bit 44 TOE Queue 44 Full Interrupt unsigned int toe_q45_full : 1; // bit 45 TOE Queue 45 Full Interrupt unsigned int toe_q46_full : 1; // bit 46 TOE Queue 46 Full Interrupt unsigned int toe_q47_full : 1; // bit 47 TOE Queue 47 Full Interrupt unsigned int toe_q48_full : 1; // bit 48 TOE Queue 48 Full Interrupt unsigned int toe_q49_full : 1; // bit 49 TOE Queue 49 Full Interrupt unsigned int toe_q50_full : 1; // bit 50 TOE Queue 50 Full Interrupt unsigned int toe_q51_full : 1; // bit 51 TOE Queue 51 Full Interrupt unsigned int toe_q52_full : 1; // bit 52 TOE Queue 52 Full Interrupt unsigned int toe_q53_full : 1; // bit 53 TOE Queue 53 Full Interrupt unsigned int toe_q54_full : 1; // bit 54 TOE Queue 54 Full Interrupt unsigned int toe_q55_full : 1; // bit 55 TOE Queue 55 Full Interrupt unsigned int toe_q56_full : 1; // bit 56 TOE Queue 56 Full Interrupt unsigned int toe_q57_full : 1; // bit 57 TOE Queue 57 Full Interrupt unsigned int toe_q58_full : 1; // bit 58 TOE Queue 58 Full Interrupt unsigned int toe_q59_full : 1; // bit 59 TOE Queue 59 Full Interrupt unsigned int toe_q60_full : 1; // bit 60 TOE Queue 60 Full Interrupt unsigned int toe_q61_full : 1; // bit 61 TOE Queue 61 Full Interrupt unsigned int toe_q62_full : 1; // bit 62 TOE Queue 62 Full Interrupt unsigned int toe_q63_full : 1; // bit 63 TOE Queue 63 Full Interrupt#endif } bits;} INTR_REG3_T;#define TOE_QH_FULL_INT_BIT(x) BIT(x-32)/********************************************************************** * Interrupt Status Register 4 (offset 0x0060) * Interrupt Mask Register 4 (offset 0x0064) * Interrupt Select Register 4 (offset 0x0068) **********************************************************************/typedef union{ unsigned char byte; struct bit_0060 {#if (BIG_ENDIAN==1) unsigned char reserved : 1; // unsigned char cnt_full : 1; // MIB counters half full interrupt unsigned char rx_pause_on : 1; // received pause on frame interrupt unsigned char tx_pause_on : 1; // transmit pause on frame interrupt unsigned char rx_pause_off : 1; // received pause off frame interrupt unsigned char tx_pause_off : 1; // received pause off frame interrupt unsigned char rx_overrun : 1; // GMAC Rx FIFO overrun interrupt unsigned char status_changed: 1; // Status Changed Intr for RGMII Mode#else unsigned char status_changed: 1; // Status Changed Intr for RGMII Mode unsigned char rx_overrun : 1; // GMAC Rx FIFO overrun interrupt unsigned char tx_pause_off : 1; // received pause off frame interrupt unsigned char rx_pause_off : 1; // received pause off frame interrupt unsigned char tx_pause_on : 1; // transmit pause on frame interrupt unsigned char rx_pause_on : 1; // received pause on frame interrupt unsigned char cnt_full : 1; // MIB counters half full interrupt unsigned char reserved : 1; // #endif } _PACKED_ bits;} _PACKED_ GMAC_INTR_T; typedef union{ unsigned int bits32; struct bit_0060_2 {#if (BIG_ENDIAN==1) GMAC_INTR_T gmac1; GMAC_INTR_T gmac0; unsigned int class_qf_int: 14; // bit 15:2 Classification Rx Queue13-0 Full Intr. unsigned int hwfq_empty : 1; // bit 1 Hardware Free Queue Empty Intr. unsigned int swfq_empty : 1; // bit 0 Software Free Queue Empty Intr.#else#endif unsigned int swfq_empty : 1; // bit 0 Software Free Queue Empty Intr. unsigned int hwfq_empty : 1; // bit 1 Hardware Free Queue Empty Intr. unsigned int class_qf_int: 14; // bit 15:2 Classification Rx Queue13-0 Full Intr. GMAC_INTR_T gmac0; GMAC_INTR_T gmac1; } bits;} INTR_REG4_T;#define GMAC1_RESERVED_INT_BIT BIT(31)#define GMAC1_MIB_INT_BIT BIT(30)#define GMAC1_RX_PAUSE_ON_INT_BIT BIT(29)#define GMAC1_TX_PAUSE_ON_INT_BIT BIT(28)#define GMAC1_RX_PAUSE_OFF_INT_BIT BIT(27)#define GMAC1_TX_PAUSE_OFF_INT_BIT BIT(26)#define GMAC1_RX_OVERRUN_INT_BIT BIT(25)#define GMAC1_STATUS_CHANGE_INT_BIT BIT(24)#define GMAC0_RESERVED_INT_BIT BIT(23)#define GMAC0_MIB_INT_BIT BIT(22)#define GMAC0_RX_PAUSE_ON_INT_BIT BIT(21)#define GMAC0_TX_PAUSE_ON_INT_BIT BIT(20)#define GMAC0_RX_PAUSE_OFF_INT_BIT BIT(19)#define GMAC0_TX_PAUSE_OFF_INT_BIT BIT(18)#define GMAC0_RX_OVERRUN_INT_BIT BIT(17)#define GMAC0_STATUS_CHANGE_INT_BIT BIT(16)#define CLASS_RX_FULL_INT_BIT(x) BIT((x+2))#define HWFQ_EMPTY_INT_BIT BIT(1)#define SWFQ_EMPTY_INT_BIT BIT(0)/********************************************************************** * GLOBAL_QUEUE_THRESHOLD_REG (offset 0x0070) **********************************************************************/typedef union{ unsigned int bits32; struct bit_0070_2 {#if (BIG_ENDIAN==1) unsigned int toe_class : 8; // 31:24 unsigned int intrq : 8; // 23:16 unsigned int hwfq_empty : 8; // 15:8 Hardware Free Queue Empty Threshold unsigned int swfq_empty : 8; // 7:0 Software Free Queue Empty Threshold#else#endif unsigned int swfq_empty : 8; // 7:0 Software Free Queue Empty Threshold unsigned int hwfq_empty : 8; // 15:8 Hardware Free Queue Empty Threshold unsigned int intrq : 8; // 23:16 unsigned int toe_class : 8; // 31:24 } bits;} QUEUE_THRESHOLD_T;/********************************************************************** * GMAC DMA Control Register * GMAC0 offset 0x8000 * GMAC1 offset 0xC000 **********************************************************************/typedef union{ unsigned int bits32; struct bit_8000 {#if (BIG_ENDIAN==1) unsigned int rd_enable : 1; // bit 31 Rx DMA Enable unsigned int td_enable : 1; // bit 30 Tx DMA Enable unsigned int loopback : 1; // bit 29 Loopback TxDMA to RxDMA unsigned int drop_small_ack : 1; // bit 28 1: Drop, 0: Accept unsigned int reserved : 10; // bit 27:18 unsigned int rd_insert_bytes : 2; // bit 17:16 unsigned int rd_prot : 4; // bit 15:12 DMA Protection Control unsigned int rd_burst_size : 2; // bit 11:10 DMA max burst size for every AHB request unsigned int rd_bus : 2; // bit 9:8 Peripheral Bus Width unsigned int td_prot : 4; // bit 7:4 TxDMA protection control unsigned int td_burst_size : 2; // bit 3:2 TxDMA max burst size for every AHB request unsigned int td_bus : 2; // bit 1:0 Peripheral Bus Width#else unsigned int td_bus : 2; // bit 1:0 Peripheral Bus Width unsigned int td_burst_size : 2; // bit 3:2 TxDMA max burst size for every AHB request unsigned int td_prot : 4; // bit 7:4 TxDMA protection control unsigned int rd_bus : 2; // bit 9:8 Peripheral Bus Width unsigned int rd_burst_size : 2; // bit 11:10 DMA max burst size for every AHB request unsigned int rd_prot : 4; // bit 15:12 DMA Protection Control unsigned int rd_insert_bytes : 2; // bit 17:16 unsigned int reserved : 10; // bit 27:18 unsigned int drop_small_ack : 1; // bit 28 1: Drop, 0: Accept unsigned int loopback : 1; // bit 29 Loopback TxDMA to RxDMA unsigned int td_enable : 1; // bit 30 Tx DMA Enable unsigned int rd_enable : 1; // bit 31 Rx DMA Enable#endif } bits;} GMAC_DMA_CTRL_T;/********************************************************************** * GMAC Tx Weighting Control Register 0 * GMAC0 offset 0x8004 * GMAC1 offset 0xC004 **********************************************************************/typedef union{ unsigned int bits32; struct bit_8004⌨️ 快捷键说明
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