sl_lepus_gmac.h

某个ARM9板子的实际bootloader 对裁剪

    // These are general status information:
    unsigned int speed;                 // 10,000,000 or 100,000,000
                                        //     to infinity and beyond?

    // These are typically kept by device hardware - and there may be some
    // cost for getting up to date values:

    unsigned int supports_dot3;  /* Boolean value if the device supports dot3*/
    unsigned int tx_good;
    unsigned int tx_max_collisions;
    unsigned int tx_late_collisions;
    unsigned int tx_underrun;
    unsigned int tx_carrier_loss;
    unsigned int tx_deferred;
    unsigned int tx_sqetesterrors;
    unsigned int tx_single_collisions;
    unsigned int tx_mult_collisions;
    unsigned int tx_total_collisions;
    unsigned int rx_good;
    unsigned int rx_crc_errors;
    unsigned int rx_align_errors;
    unsigned int rx_resource_errors;
    unsigned int rx_overrun_errors;
    unsigned int rx_collisions;
    unsigned int rx_short_frames;
    unsigned int rx_too_long_frames;
    unsigned int rx_symbol_errors;

    // These are typically kept by driver software:
    unsigned int interrupts;
    unsigned int rx_count;
    unsigned int rx_deliver;
    unsigned int rx_resource;
    unsigned int rx_restart;
    unsigned int tx_queue_len;
    unsigned int tx_count;
    unsigned int tx_complete;
    unsigned int tx_dropped;

    // Add any others here...

};

/**********************************************************************
 * TOE version Register (offset 0x0000)
 **********************************************************************/
typedef union
{
	unsigned int bits32;
	struct bit
	{
#if (BIG_ENDIAN==1)
		
		unsigned int reserved		: 15;	// bit 31:17
		unsigned int v_bit_mode		: 1;	// bit 16		1: 128-entry
		unsigned int device_id		: 12;	// bit 15:4 	Device ID
		unsigned int revision_id	: 4;	// bit  3:0 	Revision ID
#else
		unsigned int revision_id	: 4;	// bit  3:0 	Revision ID
		unsigned int device_id		: 12;	// bit 15:4 	Device ID
		unsigned int v_bit_mode		: 1;	// bit 16		1: 128-entry
		unsigned int reserved		: 15;	// bit 31:17
#endif
	} bits;
} TOE_VERSION_T;


/**********************************************************************
 * DMA Queues description Ring Base Address/Size Register (offset 0x0004)
 **********************************************************************/
typedef union
{
	unsigned int bits32;
	unsigned int base_size;
} DMA_Q_BASE_SIZE_T;
#define DMA_Q_BASE_MASK 	(~0x0f)

/**********************************************************************
 * DMA SKB Buffer register (offset 0x0008)
 **********************************************************************/
typedef union
{
	unsigned int bits32;
	struct bit_0008
	{
#if (BIG_ENDIAN==1)
		
		unsigned int hw_skb_size	: 16;	// bit 31:16	HW Free poll SKB Size
		unsigned int sw_skb_size	: 16;	// bit 15:0 	SW Free poll SKB Size
#else
		unsigned int sw_skb_size	: 16;	// bit 15:0 	SW Free poll SKB Size
		unsigned int hw_skb_size	: 16;	// bit 31:16	HW Free poll SKB Size
#endif
	} bits;
} DMA_SKB_SIZE_T;

/**********************************************************************
 * DMA SW Free Queue Read/Write Pointer Register (offset 0x000C)
 **********************************************************************/
typedef union
{
	unsigned int bits32;
	struct bit_000c
	{
#if (BIG_ENDIAN==1)
		
		unsigned int wptr			: 16;	// bit 31:16 	Write Ptr, RW
		unsigned int rptr			: 16;	// bit 15:0		Read Ptr, RO
#else
		unsigned int rptr			: 16;	// bit 15:0		Read Ptr, RO
		unsigned int wptr			: 16;	// bit 31:16 	Write Ptr, RW
#endif
	} bits;
} DMA_RWPTR_T;

/**********************************************************************
 * DMA HW Free Queue Read/Write Pointer Register (offset 0x0010)
 **********************************************************************/
// see DMA_RWPTR_T structure

/**********************************************************************
 * Interrupt Status Register 0 	(offset 0x0020)
 * Interrupt Mask Register 0 	(offset 0x0024)
 * Interrupt Select Register 0 	(offset 0x0028)
 **********************************************************************/
typedef union
{
	unsigned int bits32;
	struct bit_0020
	{
#if (BIG_ENDIAN==1)
		unsigned int txDerr1		: 1;	// bit 31	GMAC1 AHB Bus Error while Tx
		unsigned int txPerr1		: 1;	// bit 30	GMAC1 Tx Descriptor Protocol Error
		unsigned int txDerr0		: 1;	// bit 29	GMAC0 AHB Bus Error while Tx
		unsigned int txPerr0		: 1;	// bit 28	GMAC0 Tx Descriptor Protocol Error
		unsigned int rxDerr1		: 1;	// bit 27	GMAC1 AHB Bus Error while Rx
		unsigned int rxPerr1		: 1;	// bit 26	GMAC1 Rx Descriptor Protocol Error
		unsigned int rxDerr0		: 1;	// bit 25	GMAC0 AHB Bus Error while Rx
		unsigned int rxPerr0		: 1;	// bit 24	GMAC0 Rx Descriptor Protocol Error
		unsigned int swtq15_fin		: 1;	// bit 23	GMAC1 SW Tx Queue 5 Finish Interrupt
		unsigned int swtq14_fin		: 1;	// bit 22	GMAC1 SW Tx Queue 4 Finish Interrupt
		unsigned int swtq13_fin		: 1;	// bit 21	GMAC1 SW Tx Queue 3 Finish Interrupt
		unsigned int swtq12_fin		: 1;	// bit 20	GMAC1 SW Tx Queue 2 Finish Interrupt
		unsigned int swtq11_fin		: 1;	// bit 19	GMAC1 SW Tx Queue 1 Finish Interrupt
		unsigned int swtq10_fin		: 1;	// bit 18	GMAC1 SW Tx Queue 0 Finish Interrupt
		unsigned int swtq05_fin		: 1;	// bit 17	GMAC0 SW Tx Queue 5 Finish Interrupt
		unsigned int swtq04_fin		: 1;	// bit 16	GMAC0 SW Tx Queue 4 Finish Interrupt
		unsigned int swtq03_fin		: 1;	// bit 15	GMAC0 SW Tx Queue 3 Finish Interrupt
		unsigned int swtq02_fin		: 1;	// bit 14	GMAC0 SW Tx Queue 2 Finish Interrupt
		unsigned int swtq01_fin		: 1;	// bit 13	GMAC0 SW Tx Queue 1 Finish Interrupt
		unsigned int swtq00_fin		: 1;	// bit 12	GMAC0 SW Tx Queue 0 Finish Interrupt
		unsigned int swtq15_eof		: 1;	// bit 11	GMAC1 SW Tx Queue 5 EOF Interrupt
		unsigned int swtq14_eof		: 1;	// bit 10	GMAC1 SW Tx Queue 4 EOF Interrupt
		unsigned int swtq13_eof		: 1;	// bit 9	GMAC1 SW Tx Queue 3 EOF Interrupt
		unsigned int swtq12_eof		: 1;	// bit 8	GMAC1 SW Tx Queue 2 EOF Interrupt
		unsigned int swtq11_eof		: 1;	// bit 7	GMAC1 SW Tx Queue 1 EOF Interrupt
		unsigned int swtq10_eof		: 1;	// bit 6	GMAC1 SW Tx Queue 0 EOF Interrupt
		unsigned int swtq05_eof		: 1;	// bit 5	GMAC0 SW Tx Queue 5 EOF Interrupt
		unsigned int swtq04_eof		: 1;	// bit 4	GMAC0 SW Tx Queue 4 EOF Interrupt
		unsigned int swtq03_eof		: 1;	// bit 3	GMAC0 SW Tx Queue 3 EOF Interrupt
		unsigned int swtq02_eof		: 1;	// bit 2	GMAC0 SW Tx Queue 2 EOF Interrupt
		unsigned int swtq01_eof		: 1;	// bit 1	GMAC0 SW Tx Queue 1 EOF Interrupt
		unsigned int swtq00_eof		: 1;	// bit 0	GMAC0 SW Tx Queue 0 EOF Interrupt
#else
		unsigned int swtq00_eof		: 1;	// bit 0	GMAC0 SW Tx Queue 0 EOF Interrupt
		unsigned int swtq01_eof		: 1;	// bit 1	GMAC0 SW Tx Queue 1 EOF Interrupt
		unsigned int swtq02_eof		: 1;	// bit 2	GMAC0 SW Tx Queue 2 EOF Interrupt
		unsigned int swtq03_eof		: 1;	// bit 3	GMAC0 SW Tx Queue 3 EOF Interrupt
		unsigned int swtq04_eof		: 1;	// bit 4	GMAC0 SW Tx Queue 4 EOF Interrupt
		unsigned int swtq05_eof		: 1;	// bit 5	GMAC0 SW Tx Queue 5 EOF Interrupt
		unsigned int swtq10_eof		: 1;	// bit 6	GMAC1 SW Tx Queue 0 EOF Interrupt
		unsigned int swtq11_eof		: 1;	// bit 7	GMAC1 SW Tx Queue 1 EOF Interrupt
		unsigned int swtq12_eof		: 1;	// bit 8	GMAC1 SW Tx Queue 2 EOF Interrupt
		unsigned int swtq13_eof		: 1;	// bit 9	GMAC1 SW Tx Queue 3 EOF Interrupt
		unsigned int swtq14_eof		: 1;	// bit 10	GMAC1 SW Tx Queue 4 EOF Interrupt
		unsigned int swtq15_eof		: 1;	// bit 11	GMAC1 SW Tx Queue 5 EOF Interrupt
		unsigned int swtq00_fin		: 1;	// bit 12	GMAC0 SW Tx Queue 0 Finish Interrupt
		unsigned int swtq01_fin		: 1;	// bit 13	GMAC0 SW Tx Queue 1 Finish Interrupt
		unsigned int swtq02_fin		: 1;	// bit 14	GMAC0 SW Tx Queue 2 Finish Interrupt
		unsigned int swtq03_fin		: 1;	// bit 15	GMAC0 SW Tx Queue 3 Finish Interrupt
		unsigned int swtq04_fin		: 1;	// bit 16	GMAC0 SW Tx Queue 4 Finish Interrupt
		unsigned int swtq05_fin		: 1;	// bit 17	GMAC0 SW Tx Queue 5 Finish Interrupt
		unsigned int swtq10_fin		: 1;	// bit 18	GMAC1 SW Tx Queue 0 Finish Interrupt
		unsigned int swtq11_fin		: 1;	// bit 19	GMAC1 SW Tx Queue 1 Finish Interrupt
		unsigned int swtq12_fin		: 1;	// bit 20	GMAC1 SW Tx Queue 2 Finish Interrupt
		unsigned int swtq13_fin		: 1;	// bit 21	GMAC1 SW Tx Queue 3 Finish Interrupt
		unsigned int swtq14_fin		: 1;	// bit 22	GMAC1 SW Tx Queue 4 Finish Interrupt
		unsigned int swtq15_fin		: 1;	// bit 23	GMAC1 SW Tx Queue 5 Finish Interrupt
		unsigned int rxPerr0		: 1;	// bit 24	GMAC0 Rx Descriptor Protocol Error
		unsigned int rxDerr0		: 1;	// bit 25	GMAC0 AHB Bus Error while Rx
		unsigned int rxPerr1		: 1;	// bit 26	GMAC1 Rx Descriptor Protocol Error
		unsigned int rxDerr1		: 1;	// bit 27	GMAC1 AHB Bus Error while Rx
		unsigned int txPerr0		: 1;	// bit 28	GMAC0 Tx Descriptor Protocol Error
		unsigned int txDerr0		: 1;	// bit 29	GMAC0 AHB Bus Error while Tx
		unsigned int txPerr1		: 1;	// bit 30	GMAC1 Tx Descriptor Protocol Error
		unsigned int txDerr1		: 1;	// bit 31	GMAC1 AHB Bus Error while Tx
#endif
	} bits;
} INTR_REG0_T;

#define GMAC1_TXDERR_INT_BIT		BIT(31)
#define GMAC1_TXPERR_INT_BIT		BIT(30)
#define GMAC0_TXDERR_INT_BIT		BIT(29)
#define GMAC0_TXPERR_INT_BIT		BIT(28)
#define GMAC1_RXDERR_INT_BIT		BIT(27)
#define GMAC1_RXPERR_INT_BIT		BIT(26)
#define GMAC0_RXDERR_INT_BIT		BIT(25)
#define GMAC0_RXPERR_INT_BIT		BIT(24)
#define GMAC1_SWTQ15_FIN_INT_BIT	BIT(23)
#define GMAC1_SWTQ14_FIN_INT_BIT	BIT(22)
#define GMAC1_SWTQ13_FIN_INT_BIT	BIT(21)
#define GMAC1_SWTQ12_FIN_INT_BIT	BIT(20)
#define GMAC1_SWTQ11_FIN_INT_BIT	BIT(19)
#define GMAC1_SWTQ10_FIN_INT_BIT	BIT(18)
#define GMAC0_SWTQ05_FIN_INT_BIT	BIT(17)
#define GMAC0_SWTQ04_FIN_INT_BIT	BIT(16)
#define GMAC0_SWTQ03_FIN_INT_BIT	BIT(15)
#define GMAC0_SWTQ02_FIN_INT_BIT	BIT(14)
#define GMAC0_SWTQ01_FIN_INT_BIT	BIT(13)
#define GMAC0_SWTQ00_FIN_INT_BIT	BIT(12)
#define GMAC1_SWTQ15_EOF_INT_BIT	BIT(11)
#define GMAC1_SWTQ14_EOF_INT_BIT	BIT(10)
#define GMAC1_SWTQ13_EOF_INT_BIT	BIT(9)
#define GMAC1_SWTQ12_EOF_INT_BIT	BIT(8)
#define GMAC1_SWTQ11_EOF_INT_BIT	BIT(7)
#define GMAC1_SWTQ10_EOF_INT_BIT	BIT(6)
#define GMAC0_SWTQ05_EOF_INT_BIT	BIT(5)
#define GMAC0_SWTQ04_EOF_INT_BIT	BIT(4)
#define GMAC0_SWTQ03_EOF_INT_BIT	BIT(3)
#define GMAC0_SWTQ02_EOF_INT_BIT	BIT(2)
#define GMAC0_SWTQ01_EOF_INT_BIT	BIT(1)
#define GMAC0_SWTQ00_EOF_INT_BIT	BIT(0)


/**********************************************************************
 * Interrupt Status Register 1 	(offset 0x0030)
 * Interrupt Mask Register 1 	(offset 0x0034)
 * Interrupt Select Register 1 	(offset 0x0038)
 **********************************************************************/
typedef union
{
	unsigned int bits32;
	struct bit_0030
	{
#if (BIG_ENDIAN==1)
		unsigned int toe_iq3_full	: 1;	// bit 31	TOE Interrupt Queue 3 Full Interrupt
		unsigned int toe_iq2_full	: 1;	// bit 30	TOE Interrupt Queue 2 Full Interrupt
		unsigned int toe_iq1_full	: 1;	// bit 29	TOE Interrupt Queue 1 Full Interrupt
		unsigned int toe_iq0_full	: 1;	// bit 28	TOE Interrupt Queue 0 Full Interrupt
		unsigned int toe_iq3_intr	: 1;	// bit 27	TOE Interrupt Queue 3 with Interrupts
		unsigned int toe_iq2_intr	: 1;	// bit 26	TOE Interrupt Queue 2 with Interrupts
		unsigned int toe_iq1_intr	: 1;	// bit 25	TOE Interrupt Queue 1 with Interrupts
		unsigned int toe_iq0_intr	: 1;	// bit 24	TOE Interrupt Queue 0 with Interrupts
		unsigned int hwtq13_eof		: 1;	// bit 23	GMAC1 HW Tx Queue3 EOF Interrupt
		unsigned int hwtq12_eof		: 1;	// bit 22	GMAC1 HW Tx Queue2 EOF Interrupt
		unsigned int hwtq11_eof		: 1;	// bit 21	GMAC1 HW Tx Queue1 EOF Interrupt
		unsigned int hwtq10_eof		: 1;	// bit 20	GMAC1 HW Tx Queue0 EOF Interrupt
		unsigned int hwtq03_eof		: 1;	// bit 19	GMAC0 HW Tx Queue3 EOF Interrupt
		unsigned int hwtq02_eof		: 1;	// bit 18	GMAC0 HW Tx Queue2 EOF Interrupt
		unsigned int hwtq01_eof		: 1;	// bit 17	GMAC0 HW Tx Queue1 EOF Interrupt
		unsigned int hwtq00_eof		: 1;	// bit 16	GMAC0 HW Tx Queue0 EOF Interrupt
		unsigned int class_rx		: 14;	// bit 15:2	Classification Queue Rx Interrupt
		unsigned int default_q1_eof	: 1;	// bit 1	Default Queue 1 EOF Interrupt
		unsigned int default_q0_eof	: 1;	// bit 0	Default Queue 0 EOF Interrupt
#else
		unsigned int default_q0_eof	: 1;	// bit 0	Default Queue 0 EOF Interrupt
		unsigned int default_q1_eof	: 1;	// bit 1	Default Queue 1 EOF Interrupt
		unsigned int class_rx		: 14;	// bit 15:2	Classification Queue Rx Interrupt
		unsigned int hwtq00_eof		: 1;	// bit 16	GMAC0 HW Tx Queue0 EOF Interrupt
		unsigned int hwtq01_eof		: 1;	// bit 17	GMAC0 HW Tx Queue1 EOF Interrupt
		unsigned int hwtq02_eof		: 1;	// bit 18	GMAC0 HW Tx Queue2 EOF Interrupt
		unsigned int hwtq03_eof		: 1;	// bit 19	GMAC0 HW Tx Queue3 EOF Interrupt
		unsigned int hwtq10_eof		: 1;	// bit 20	GMAC1 HW Tx Queue0 EOF Interrupt
		unsigned int hwtq11_eof		: 1;	// bit 21	GMAC1 HW Tx Queue1 EOF Interrupt
		unsigned int hwtq12_eof		: 1;	// bit 22	GMAC1 HW Tx Queue2 EOF Interrupt
		unsigned int hwtq13_eof		: 1;	// bit 23	GMAC1 HW Tx Queue3 EOF Interrupt
		unsigned int toe_iq0_intr	: 1;	// bit 24	TOE Interrupt Queue 0 with Interrupts
		unsigned int toe_iq1_intr	: 1;	// bit 25	TOE Interrupt Queue 1 with Interrupts
		unsigned int toe_iq2_intr	: 1;	// bit 26	TOE Interrupt Queue 2 with Interrupts
		unsigned int toe_iq3_intr	: 1;	// bit 27	TOE Interrupt Queue 3 with Interrupts
		unsigned int toe_iq0_full	: 1;	// bit 28	TOE Interrupt Queue 0 Full Interrupt
		unsigned int toe_iq1_full	: 1;	// bit 29	TOE Interrupt Queue 1 Full Interrupt
		unsigned int toe_iq2_full	: 1;	// bit 30	TOE Interrupt Queue 2 Full Interrupt
		unsigned int toe_iq3_full	: 1;	// bit 31	TOE Interrupt Queue 3 Full Interrupt
#endif
	} bits;
} INTR_REG1_T;

#define TOE_IQ3_FULL_INT_BIT		BIT(31)
#define TOE_IQ2_FULL_INT_BIT		BIT(30)
#define TOE_IQ1_FULL_INT_BIT		BIT(29)
#define TOE_IQ0_FULL_INT_BIT		BIT(28)
#define TOE_IQ3_INT_BIT				BIT(27)
#define TOE_IQ2_INT_BIT				BIT(26)
#define TOE_IQ1_INT_BIT				BIT(25)
#define TOE_IQ0_INT_BIT				BIT(24)
#define GMAC1_HWTQ13_EOF_INT_BIT	BIT(23)
#define GMAC1_HWTQ12_EOF_INT_BIT	BIT(22)
#define GMAC1_HWTQ11_EOF_INT_BIT	BIT(21)
#define GMAC1_HWTQ10_EOF_INT_BIT	BIT(20)
#define GMAC0_HWTQ03_EOF_INT_BIT	BIT(19)
#define GMAC0_HWTQ02_EOF_INT_BIT	BIT(18)
#define GMAC0_HWTQ01_EOF_INT_BIT	BIT(17)
#define GMAC0_HWTQ00_EOF_INT_BIT	BIT(16)
#define CLASS_RX_INT_BIT(x)			BIT((x+2))
#define DEFAULT_Q1_INT_BIT			BIT(1)
#define DEFAULT_Q0_INT_BIT			BIT(0)