sl_lepus_gmac.h

某个ARM9板子的实际bootloader 对裁剪

/****************************************************************************
* Copyright  Storlink Corp 2005.  All rights reserved.                
*--------------------------------------------------------------------------
* Name			: gmac_sl_lepus.h
* Description	: 
*		Define for device driver of Storlink Lepus network Engine
*
* History
*
*	Date		Writer		Description
*	-----------	-----------	-------------------------------------------------
*	08/22/2005	Gary Chen	Create and implement
*
****************************************************************************/
#ifndef _GMAC_SL_LEPUS_H
#define _GMAC_SL_LEPUS_H

#undef BIG_ENDIAN
#define BIG_ENDIAN  				0
#define GMAC_DEBUG      			1

//#define GMAC_NUM					0 

#define _PACKED_					__attribute__ ((aligned(1), packed))
typedef unsigned int				dma_addr_t;

#ifndef BIT
#define BIT(x)						(1 << (x))
#endif

#define	printk						printf
#define debug_printf				printf        			
#define IO_ADDRESS(x)				(x)
#define readl(addr)					REG32(addr)
#define writel(value, addr)			REG32(addr) = value
#define __pa(x)						(x)
#define DMA_MALLOC(size,handle)		((u32)malloc(size+15) & ~15)
#define DMA_MFREE(mem,size,handle)	free(mem)

/* define chip information */
#define DRV_NAME					"StorLink Lepus"
#define DRV_VERSION					"0.0.1"
#define LEPUS_DRIVER_NAME			DRV_NAME " Ethernet driver " DRV_VERSION

// Define frame size
#define ETHER_ADDR_LEN				6
#define GMAC_MAX_ETH_FRAME_SIZE		1514
#define GMAC_TX_BUF_SIZE			((GMAC_MAX_ETH_FRAME_SIZE + 31) & (~31))
#define MAX_ETH_FRAME_SIZE			1536  //2048
#define RX_BUF_SIZE					MAX_ETH_FRAME_SIZE

/**********************************************************************
 * Base Register
 **********************************************************************/
#define TOE_BASE					(IO_ADDRESS(SL2312_TOE_BASE))
#define GMAC_GLOBAL_BASE_ADDR       (IO_ADDRESS(SL2312_GLOBAL_BASE))
#define TOE_GLOBAL_BASE				(TOE_BASE + 0x0000)
#define TOE_NONTOE_QUE_HDR_BASE		(TOE_BASE + 0x2000)
#define TOE_TOE_QUE_HDR_BASE		(TOE_BASE + 0x3000)
#define TOE_V_BIT_BASE				(TOE_BASE + 0x4000)
#define TOE_A_BIT_BASE				(TOE_BASE + 0x6000)
#define TOE_GMAC0_DMA_BASE			(TOE_BASE + 0x8000)
#define TOE_GMAC0_BASE				(TOE_BASE + 0xA000)
#define TOE_GMAC1_DMA_BASE			(TOE_BASE + 0xC000)
#define TOE_GMAC1_BASE				(TOE_BASE + 0xE000)

/**********************************************************************
 * Queue ID
 **********************************************************************/
#define TOE_SW_FREE_QID				0x00
#define TOE_HW_FREE_QID				0x01
#define TOE_GMAC0_SW_TXQ0_QID		0x02
#define TOE_GMAC0_SW_TXQ1_QID		0x03
#define TOE_GMAC0_SW_TXQ2_QID		0x04
#define TOE_GMAC0_SW_TXQ3_QID		0x05
#define TOE_GMAC0_SW_TXQ4_QID		0x06
#define TOE_GMAC0_SW_TXQ5_QID		0x07
#define TOE_GMAC0_HW_TXQ0_QID		0x08
#define TOE_GMAC0_HW_TXQ1_QID		0x09
#define TOE_GMAC0_HW_TXQ2_QID		0x0A
#define TOE_GMAC0_HW_TXQ3_QID		0x0B
#define TOE_GMAC1_SW_TXQ0_QID		0x12
#define TOE_GMAC1_SW_TXQ1_QID		0x13
#define TOE_GMAC1_SW_TXQ2_QID		0x14
#define TOE_GMAC1_SW_TXQ3_QID		0x15
#define TOE_GMAC1_SW_TXQ4_QID		0x16
#define TOE_GMAC1_SW_TXQ5_QID		0x17
#define TOE_GMAC1_HW_TXQ0_QID		0x18
#define TOE_GMAC1_HW_TXQ1_QID		0x19
#define TOE_GMAC1_HW_TXQ2_QID		0x1A
#define TOE_GMAC1_HW_TXQ3_QID		0x1B
#define TOE_GMAC0_DEFAULT_QID		0x20
#define TOE_GMAC1_DEFAULT_QID		0x21
#define TOE_CLASSIFICATION_QID(x)	(0x22 + x)	// 0x22 ~ 0x2F
#define TOE_TOE_QID(x)				(0x40 + x)	// 0x40 ~ 0x7F

/**********************************************************************
 * TOE DMA Queue Number should be 2^n, n = 6...12
 * TOE DMA Queues are the following queue types:
 *		SW Free Queue, HW Free Queue, 
 *		GMAC 0/1 SW TX Q0-5, and GMAC 0/1 HW TX Q0-5
 * They have same descriptor numbers.
 * The base address and descriptor number are configured at
 * DMA Queues Descriptor Ring Base Address/Size Register (offset 0x0004)
 **********************************************************************/
#define TOE_SW_FREEQ_DESC_POWER		10
#define TOE_SW_FREEQ_DESC_NUM		(1<<TOE_SW_FREEQ_DESC_POWER)
#define TOE_HW_FREEQ_DESC_POWER		6
#define TOE_HW_FREEQ_DESC_NUM		(1<<TOE_HW_FREEQ_DESC_POWER)
#define TOE_GMAC0_SWTXQ_DESC_POWER	6
#define TOE_GMAC0_SWTXQ_DESC_NUM	(1<<TOE_GMAC0_SWTXQ_DESC_POWER)
#define TOE_GMAC0_HWTXQ_DESC_POWER	TOE_HW_FREEQ_DESC_POWER
#define TOE_GMAC0_HWTXQ_DESC_NUM	(1<<TOE_GMAC0_HWTXQ_DESC_POWER)
#define TOE_GMAC1_SWTXQ_DESC_POWER	6
#define TOE_GMAC1_SWTXQ_DESC_NUM	(1<<TOE_GMAC1_SWTXQ_DESC_POWER)
#define TOE_GMAC1_HWTXQ_DESC_POWER	TOE_HW_FREEQ_DESC_POWER
#define TOE_GMAC1_HWTXQ_DESC_NUM	(1<<TOE_GMAC1_HWTXQ_DESC_POWER)
#define TOE_DEFAULT_Q0_DESC_POWER	10
#define TOE_DEFAULT_Q0_DESC_NUM		(1<<TOE_DEFAULT_Q0_DESC_POWER)
#define TOE_DEFAULT_Q1_DESC_POWER	10
#define TOE_DEFAULT_Q1_DESC_NUM		(1<<TOE_DEFAULT_Q1_DESC_POWER)
#define TOE_TOE_DESC_POWER			6
#define TOE_TOE_DESC_NUM			(1<<TOE_TOE_DESC_POWER)
#define TOE_CLASS_DESC_POWER		6
#define TOE_CLASS_DESC_NUM			(1<<TOE_CLASS_DESC_POWER)
#define TOE_INTR_DESC_POWER			6
#define TOE_INTR_DESC_NUM			(1<<TOE_INTR_DESC_POWER)

#define TOE_TOE_QUEUE_MAX			64
#define TOE_TOE_QUEUE_NUM			64
#define TOE_CLASS_QUEUE_MAX			14
#define TOE_CLASS_QUEUE_NUM			14
#define TOE_INTR_QUEUE_MAX			0//4
#define TOE_INTR_QUEUE_NUM			0//4
#define TOE_SW_TXQ_NUM				1//6
#define TOE_HW_TXQ_NUM				1//4

#define RX_DESC_NUM					TOE_DEFAULT_Q0_DESC_NUM
#define TX_DESC_NUM					max(TOE_GMAC0_SWTXQ_DESC_NUM, TOE_GMAC1_SWTXQ_DESC_NUM)

#define RWPTR_ADVANCE_ONE(x, max)	((x == (max -1)) ? 0 : x+1)
#define SET_WPTR(addr, data)		(*(volatile u16 * const)((u32)(addr)+2) = (u16)data)
#define SET_RPTR(addr, data)		(*(volatile u16 * const)((u32)(addr)) = (u16)data)

/**********************************************************************
 * Global registers
 * #define TOE_GLOBAL_BASE			(TOE_BASE + 0x0000)
 * Base 0x60000000
 **********************************************************************/
#define GLOBAL_TOE_VERSION_REG			0x0000
#define GLOBAL_SW_FREEQ_BASE_SIZE_REG	0x0004
#define GLOBAL_HW_FREEQ_BASE_SIZE_REG	0x0008
#define GLOBAL_DMA_SKB_SIZE_REG			0x0010
#define GLOBAL_SWFQ_RWPTR_REG			0x0014
#define GLOBAL_HWFQ_RWPTR_REG			0x0018
#define GLOBAL_INTERRUPT_STATUS_0_REG	0x0020
#define GLOBAL_INTERRUPT_ENABLE_0_REG	0x0024
#define GLOBAL_INTERRUPT_SELECT_0_REG	0x0028
#define GLOBAL_INTERRUPT_STATUS_1_REG	0x0030
#define GLOBAL_INTERRUPT_ENABLE_1_REG	0x0034
#define GLOBAL_INTERRUPT_SELECT_1_REG	0x0038
#define GLOBAL_INTERRUPT_STATUS_2_REG	0x0040
#define GLOBAL_INTERRUPT_ENABLE_2_REG	0x0044
#define GLOBAL_INTERRUPT_SELECT_2_REG	0x0048
#define GLOBAL_INTERRUPT_STATUS_3_REG	0x0050
#define GLOBAL_INTERRUPT_ENABLE_3_REG	0x0054
#define GLOBAL_INTERRUPT_SELECT_3_REG	0x0058
#define GLOBAL_INTERRUPT_STATUS_4_REG	0x0060
#define GLOBAL_INTERRUPT_ENABLE_4_REG	0x0064
#define GLOBAL_INTERRUPT_SELECT_4_REG	0x0068
#define GLOBAL_HASH_TABLE_BASE_REG		0x006C
#define GLOBAL_QUEUE_THRESHOLD_REG		0x0070

/**********************************************************************
 * GMAC 0/1 DMA/TOE register
 * #define TOE_GMAC0_DMA_BASE		(TOE_BASE + 0x8000)
 * #define TOE_GMAC1_DMA_BASE		(TOE_BASE + 0xC000)
 * Base 0x60008000 or 0x6000C000
 **********************************************************************/
#define GMAC_DMA_CTRL_REG				0x0000
#define GMAC_TX_WEIGHTING_CTRL_0_REG	0x0004
#define GMAC_TX_WEIGHTING_CTRL_1_REG	0x0008
#define GMAC_SW_TX_QUEUE0_PTR_REG		0x000C
#define GMAC_SW_TX_QUEUE1_PTR_REG		0x0010
#define GMAC_SW_TX_QUEUE2_PTR_REG		0x0014
#define GMAC_SW_TX_QUEUE3_PTR_REG		0x0018
#define GMAC_SW_TX_QUEUE4_PTR_REG		0x001C
#define GMAC_SW_TX_QUEUE5_PTR_REG		0x0020
#define GMAC_HW_TX_QUEUE0_PTR_REG		0x0024
#define GMAC_HW_TX_QUEUE1_PTR_REG		0x0028
#define GMAC_HW_TX_QUEUE2_PTR_REG		0x002C
#define GMAC_HW_TX_QUEUE3_PTR_REG		0x0030
#define GMAC_DMA_TX_FIRST_DESC_REG		0x0038
#define GMAC_DMA_TX_CURR_DESC_REG		0x003C
#define GMAC_DMA_TX_DESC_WORD0_REG		0x0040
#define GMAC_DMA_TX_DESC_WORD1_REG		0x0044
#define GMAC_DMA_TX_DESC_WORD2_REG		0x0048
#define GMAC_DMA_TX_DESC_WORD3_REG		0x004C
#define GMAC_SW_TX_QUEUE_BASE_REG		0x0050
#define GMAC_HW_TX_QUEUE_BASE_REG		0x0054
#define GMAC_DMA_RX_FIRST_DESC_REG		0x0058
#define GMAC_DMA_RX_CURR_DESC_REG		0x005C
#define GMAC_DMA_RX_DESC_WORD0_REG		0x0060
#define GMAC_DMA_RX_DESC_WORD1_REG		0x0064
#define GMAC_DMA_RX_DESC_WORD2_REG		0x0068
#define GMAC_DMA_RX_DESC_WORD3_REG		0x006C
#define GMAC_HASH_ENGINE_REG0			0x0070
#define GMAC_HASH_ENGINE_REG1			0x0074
#define GMAC_MR0CR0						0x0078 	// matching rule 0 Control register 0
#define GMAC_MR0CR1						0x007C	// matching rule 0 Control register 1
#define GMAC_MR0CR2						0x0080	// matching rule 0 Control register 2
#define GMAC_MR1CR0						0x0084	// matching rule 1 Control register 0
#define GMAC_MR1CR1						0x0088	// matching rule 1 Control register 1
#define GMAC_MR1CR2						0x008C	// matching rule 1 Control register 2
#define GMAC_MR2CR0						0x0090	// matching rule 2 Control register 0
#define GMAC_MR2CR1						0x0094	// matching rule 2 Control register 1
#define GMAC_MR2CR2						0x0098	// matching rule 2 Control register 2
#define GMAC_MR3CR0						0x009C	// matching rule 3 Control register 0
#define GMAC_MR3CR1						0x00A0	// matching rule 3 Control register 1
#define GMAC_MR3CR2						0x00A4	// matching rule 3 Control register 2
#define GMAC_SPR0						0x00A8	// Support Protocol Regsister 0
#define GMAC_SPR1						0x00AC	// Support Protocol Regsister 1
#define GMAC_SPR2						0x00B0	// Support Protocol Regsister 2
#define GMAC_SPR3						0x00B4	// Support Protocol Regsister 3
#define GMAC_SPR4						0x00B8	// Support Protocol Regsister 4
#define GMAC_SPR5						0x00BC	// Support Protocol Regsister 5
#define GMAC_SPR6						0x00C0	// Support Protocol Regsister 6
#define GMAC_SPR7						0x00C4	// Support Protocol Regsister 7

/**********************************************************************
 * TOE GMAC 0/1 register
 * #define TOE_GMAC0_BASE				(TOE_BASE + 0xA000)
 * #define TOE_GMAC1_BASE				(TOE_BASE + 0xE000)
 * Base 0x6000A000 or 0x6000E000
 **********************************************************************/
enum GMAC_REGISTER {
	GMAC_STA_ADD0 	= 0x0000,
	GMAC_STA_ADD1	= 0x0004,
	GMAC_STA_ADD2	= 0x0008,
	GMAC_RX_FLTR	= 0x000c,
	GMAC_MCAST_FIL0 = 0x0010,
	GMAC_MCAST_FIL1 = 0x0014,
	GMAC_CONFIG0	= 0x0018,
	GMAC_CONFIG1	= 0x001c,
	GMAC_CONFIG2	= 0x0020,
	GMAC_CONFIG3	= 0x0024,
	GMAC_RESERVED	= 0x0028,
	GMAC_STATUS		= 0x002c,
	GMAC_IN_DISCARDS= 0x0030,
	GMAC_IN_ERRORS  = 0x0034,
	GMAC_IN_MCAST   = 0x0038,
	GMAC_IN_BCAST   = 0x003c,
	GMAC_IN_MAC1    = 0x0040,	// for STA 1 MAC Address
	GMAC_IN_MAC2    = 0x0044	// for STA 2 MAC Address
};

#define DESC_LEN (48)
#define SNMP_CHIPSET_LEN (20)


/*
 * Structure used by kernel to store most
 * addresses.
 */
struct sockaddr {
	unsigned char    sa_len;		/* total length */
	unsigned char sa_family;		/* address family */
	char	    sa_data[14];	/* actually longer; address value */
};
typedef struct sockaddr sockaddr;
/*
 * Interface request structure used for socket
 * ioctl's.  All interface ioctl's must have parameter
 * definitions which begin with ifr_name.  The
 * remainder may be interface specific.
 */
 
#define IFNAMSIZ 16
struct	ifreq {
#define IFHWADDRLEN  6
	char	ifr_name[IFNAMSIZ];		/* if name, e.g. "en0" */
	union {
		struct	sockaddr ifru_addr;
		struct	sockaddr ifru_dstaddr;
		struct	sockaddr ifru_broadaddr;
		struct	sockaddr ifru_hwaddr;
		short	ifru_flags;
		int	ifru_metric;
		char*	ifru_data;
	} ifr_ifru;
#define	ifr_addr	ifr_ifru.ifru_addr	/* address */
#define	ifr_hwaddr	ifr_ifru.ifru_hwaddr	/* MAC address */
#define	ifr_dstaddr	ifr_ifru.ifru_dstaddr	/* other end of p-to-p link */
#define	ifr_broadaddr	ifr_ifru.ifru_broadaddr	/* broadcast address */
#define	ifr_flags	ifr_ifru.ifru_flags	/* flags */
#define	ifr_metric	ifr_ifru.ifru_metric	/* metric */
#define	ifr_media	ifr_ifru.ifru_metric	/* media options (overload) */
#define	ifr_data	ifr_ifru.ifru_data	/* for use by interface */
};

struct ether_drv_stats {
    struct ifreq ifreq;                 // tell ioctl() which interface.

    char description[ DESC_LEN ];       // Textual description of hardware
    unsigned char snmp_chipset[ SNMP_CHIPSET_LEN ];
                                        // SNMP ID of chipset
    unsigned char duplex;               // 1 = UNKNOWN, 2 = SIMPLEX, 3 = DUPLEX
    unsigned char operational;          // 1 = UNKNOWN, 2 = DOWN, 3 = UP