emac_sl2312.h

某个ARM9板子的实际bootloader 对裁剪

			unsigned int buffer_size:16;	/* transfer buffer size associated with current description*/
			unsigned int desc_count : 4;	/* number of descriptors used for the current frame */
			unsigned int frame_state: 3;    /* reference Rx Status1 */
			unsigned int ucast_mac2 : 1;	/* received frame is unicast frame of MAC address 2 */
			unsigned int ucast_mac1 : 1;	/* received frame is unicast frame of MAC address 1 */
			unsigned int bcast_frame: 1;	/* received frame is broadcast frame */
			unsigned int mcast_frame: 1;	/* received frame is multicast frame */
			unsigned int vlan_tag   : 1;    /* 802.1q vlan tag packet */
			unsigned int            : 1;
			unsigned int perr		: 1;	/* protocol error during processing this descriptor */
			unsigned int derr		: 1;	/* data error during processing this descriptor */
			unsigned int own 		: 1;	/* owner bit. 0-CPU, 1-DMA */
#endif
		} bits_rx;
		
		struct bd_bits_0001
		{
#if (BIG_ENDIAN==1) 	    
			unsigned int own 		: 1;	/* owner bit. 0-CPU, 1-DMA */
			unsigned int derr		: 1;	/* data error during processing this descriptor */
			unsigned int perr		: 1;	/* protocol error during processing this descriptor */
			unsigned int            : 1;
			unsigned int coll_retry : 4;	/* collision retry count */
			unsigned int fifo_error : 1;	/* Tx FIFO Error */
			unsigned int coll_abort : 1;	/* Collision aborted */
			unsigned int late_col   : 1;	/* late collision aborted */
			unsigned int success_tx : 1;    /* successful transmitted */
			unsigned int desc_count : 4;	/* number of descriptors used for the current frame */
			unsigned int buffer_size:16;	/* transfer buffer size associated with current description*/
#else
			unsigned int buffer_size:16;	/* transfer buffer size associated with current description*/
			unsigned int desc_count : 4;	/* number of descriptors used for the current frame */
			unsigned int success_tx : 1;    /* successful transmitted */
			unsigned int late_col   : 1;	/* late collision aborted */
			unsigned int coll_abort : 1;	/* Collision aborted */
			unsigned int fifo_error : 1;	/* Tx FIFO Error */
			unsigned int coll_retry : 4;	/* collision retry count */
			unsigned int            : 1;
			unsigned int perr		: 1;	/* protocol error during processing this descriptor */
			unsigned int derr		: 1;	/* data error during processing this descriptor */
			unsigned int own 		: 1;	/* owner bit. 0-CPU, 1-DMA */
#endif
        } bits_tx;		    	
} BD_FRAME_CTRL_T;

typedef union flag_status_u
	{
		unsigned int bits32;
		struct bd_bits_0004
		{
#if (BIG_ENDIAN==1) 
            unsigned int priority   : 3;    /* user priority extracted from receiving frame*/
            unsigned int cfi        : 1;	/* cfi extracted from receiving frame*/    
			unsigned int vlan_id    :12;	/* VLAN ID extracted from receiving frame */
			unsigned int frame_count:16;	/* received frame byte count,include CRC,not include VLAN TIC */ 
#else
			unsigned int frame_count:16;	/* received frame byte count,include CRC,not include VLAN TIC */ 
			unsigned int vlan_id    :12;	/* VLAN ID extracted from receiving frame */
            unsigned int cfi        : 1;	/* cfi extracted from receiving frame*/    
            unsigned int priority   : 3;    /* user priority extracted from receiving frame*/
#endif
		} bits_rx_status;

		struct bd_bits_0005
		{
#if (BIG_ENDIAN==1) 	    
            unsigned int priority   : 3;    /* user priority to transmit*/
            unsigned int cfi        : 1;	/* cfi to transmit*/    
			unsigned int vlan_id    :12;	/* VLAN ID to transmit */
			unsigned int vlan_enable: 1;	/* VLAN TIC insertion enable */ 
			unsigned int frame_count:15;    /* total tx frame byte count */
#else
			unsigned int frame_count:15;    /* total tx frame byte count */
			unsigned int vlan_enable: 1;	/* VLAN TIC insertion enable */ 
			unsigned int vlan_id    :12;	/* VLAN ID to transmit */
            unsigned int cfi        : 1;	/* cfi to transmit*/    
            unsigned int priority   : 3;    /* user priority to transmit*/
#endif
		} bits_tx_flag;
} BD_FLAG_STATUS_T;

typedef union next_desc_u
	{
		unsigned int next_descriptor;
		struct bd_bits_000c
		{
#if (BIG_ENDIAN==1) 	    
			unsigned int ndar		:28;	/* next descriptor address */
			unsigned int eofie		: 1;	/* end of frame interrupt enable */
			unsigned int    		: 1;	 
			unsigned int sof_eof	: 2;	/* 00-the linking descriptor   01-the last descriptor of a frame*/
			                                /* 10-the first descriptor of a frame    11-only one descriptor for a frame*/
#else
			unsigned int sof_eof	: 2;	/* 00-the linking descriptor   01-the last descriptor of a frame*/
			                                /* 10-the first descriptor of a frame    11-only one descriptor for a frame*/
			unsigned int    		: 1;	 
			unsigned int eofie		: 1;	/* end of frame interrupt enable */
			unsigned int ndar		:28;	/* next descriptor address */
#endif
		} bits;                    			
} BD_NEXT_DESC_T;					        
		
typedef struct descriptor_t
{
	union frame_control_t
	{
		unsigned int bits32;
		struct bits_0000
		{
#if (BIG_ENDIAN==1) 	    
			unsigned int own 		: 1;	/* owner bit. 0-CPU, 1-DMA */
			unsigned int derr		: 1;	/* data error during processing this descriptor */
			unsigned int perr		: 1;	/* protocol error during processing this descriptor */
			unsigned int            : 1;
			unsigned int vlan_tag   : 1;    /* 802.1q vlan tag packet */
			unsigned int mcast_frame: 1;	/* received frame is multicast frame */
			unsigned int bcast_frame: 1;	/* received frame is broadcast frame */
			unsigned int ucast_mac1 : 1;	/* received frame is unicast frame of MAC address 1 */
			unsigned int ucast_mac2 : 1;	/* received frame is unicast frame of MAC address 2 */
			unsigned int frame_state: 3;    /* reference Rx Status1 */
			unsigned int desc_count : 4;	/* number of descriptors used for the current frame */
			unsigned int buffer_size:16;	/* transfer buffer size associated with current description*/
#else
			unsigned int buffer_size:16;	/* transfer buffer size associated with current description*/
			unsigned int desc_count : 4;	/* number of descriptors used for the current frame */
			unsigned int frame_state: 3;    /* reference Rx Status1 */
			unsigned int ucast_mac2 : 1;	/* received frame is unicast frame of MAC address 2 */
			unsigned int ucast_mac1 : 1;	/* received frame is unicast frame of MAC address 1 */
			unsigned int bcast_frame: 1;	/* received frame is broadcast frame */
			unsigned int mcast_frame: 1;	/* received frame is multicast frame */
			unsigned int vlan_tag   : 1;    /* 802.1q vlan tag packet */
			unsigned int            : 1;
			unsigned int perr		: 1;	/* protocol error during processing this descriptor */
			unsigned int derr		: 1;	/* data error during processing this descriptor */
			unsigned int own 		: 1;	/* owner bit. 0-CPU, 1-DMA */
#endif
		} bits_rx;
		
		struct bits_0001
		{
#if (BIG_ENDIAN==1) 	    
			unsigned int own 		: 1;	/* owner bit. 0-CPU, 1-DMA */
			unsigned int derr		: 1;	/* data error during processing this descriptor */
			unsigned int perr		: 1;	/* protocol error during processing this descriptor */
			unsigned int            : 1;
			unsigned int coll_retry : 4;	/* collision retry count */
			unsigned int fifo_error : 1;	/* Tx FIFO Error */
			unsigned int coll_abort : 1;	/* Collision aborted */
			unsigned int late_col   : 1;	/* late collision aborted */
			unsigned int success_tx : 1;    /* successful transmitted */
			unsigned int desc_count : 4;	/* number of descriptors used for the current frame */
			unsigned int buffer_size:16;	/* transfer buffer size associated with current description*/
#else
			unsigned int buffer_size:16;	/* transfer buffer size associated with current description*/
			unsigned int desc_count : 4;	/* number of descriptors used for the current frame */
			unsigned int success_tx : 1;    /* successful transmitted */
			unsigned int late_col   : 1;	/* late collision aborted */
			unsigned int coll_abort : 1;	/* Collision aborted */
			unsigned int fifo_error : 1;	/* Tx FIFO Error */
			unsigned int coll_retry : 4;	/* collision retry count */
			unsigned int            : 1;
			unsigned int perr		: 1;	/* protocol error during processing this descriptor */
			unsigned int derr		: 1;	/* data error during processing this descriptor */
			unsigned int own 		: 1;	/* owner bit. 0-CPU, 1-DMA */
#endif
        } bits_tx;		    	
	} frame_ctrl;
	
	union flag_status_t
	{
		unsigned int bits32;
		struct bits_0004
		{
#if (BIG_ENDIAN==1) 
            unsigned int priority   : 3;    /* user priority extracted from receiving frame*/
            unsigned int cfi        : 1;	/* cfi extracted from receiving frame*/    
			unsigned int vlan_id    :12;	/* VLAN ID extracted from receiving frame */
			unsigned int frame_count:16;	/* received frame byte count,include CRC,not include VLAN TIC */ 
#else
			unsigned int frame_count:16;	/* received frame byte count,include CRC,not include VLAN TIC */ 
			unsigned int vlan_id    :12;	/* VLAN ID extracted from receiving frame */
            unsigned int cfi        : 1;	/* cfi extracted from receiving frame*/    
            unsigned int priority   : 3;    /* user priority extracted from receiving frame*/
#endif
		} bits_rx_status;

		struct bits_0005
		{
#if (BIG_ENDIAN==1) 	    
            unsigned int priority   : 3;    /* user priority to transmit*/
            unsigned int cfi        : 1;	/* cfi to transmit*/    
			unsigned int vlan_id    :12;	/* VLAN ID to transmit */
			unsigned int vlan_enable: 1;	/* VLAN TIC insertion enable */ 
			unsigned int frame_count:15;    /* total tx frame byte count */
#else
			unsigned int frame_count:15;    /* total tx frame byte count */
			unsigned int vlan_enable: 1;	/* VLAN TIC insertion enable */ 
			unsigned int vlan_id    :12;	/* VLAN ID to transmit */
            unsigned int cfi        : 1;	/* cfi to transmit*/    
            unsigned int priority   : 3;    /* user priority to transmit*/
#endif
		} bits_tx_flag;
	} flag_status;

	unsigned int buf_adr;	/* data buffer address */	
	
	union next_desc_t
	{
		unsigned int next_descriptor;
		struct bits_000c
		{
#if (BIG_ENDIAN==1) 	    
			unsigned int ndar		:28;	/* next descriptor address */
			unsigned int eofie		: 1;	/* end of frame interrupt enable */
			unsigned int    		: 1;	 
			unsigned int sof_eof	: 2;	/* 00-the linking descriptor   01-the last descriptor of a frame*/
			                                /* 10-the first descriptor of a frame    11-only one descriptor for a frame*/
#else
			unsigned int sof_eof	: 2;	/* 00-the linking descriptor   01-the last descriptor of a frame*/
			                                /* 10-the first descriptor of a frame    11-only one descriptor for a frame*/
			unsigned int    		: 1;	 
			unsigned int eofie		: 1;	/* end of frame interrupt enable */
			unsigned int ndar		:28;	/* next descriptor address */
#endif
		} bits;                    			
	} next_desc;					        
} EMAC_DESCRIPTOR_T;		            	

typedef struct emac_conf {
	struct net_device *dev;
	int portmap;
	int vid;
} sys_emac_conf;
		 
typedef struct emac_private {
    unsigned char        *bufs;           /* bounce buffer region. */
    EMAC_DESCRIPTOR_T    *tx_desc;        /* point to virtual TX descriptor address*/
    EMAC_DESCRIPTOR_T    *rx_desc;        /* point to virtual RX descriptor address*/
    short 		rx_head;                          /* index of rx head */
    short 		rx_tail;                          /* index of rx tail */
    short 		tx_head;                          /* index of tx head */
    short 		tx_tail;                          /* index of tx tail */
    short 		rd_index[RX_DESC_NUM];            /* index of related rx desc */
	int			tx_err;
	unsigned char       *tx_bufs;	/* Tx bounce buffer region. */
	unsigned char       *rx_bufs;
	//EMAC_DESCRIPTOR_T	*tx_desc;	/* point to virtual TX descriptor address*/
	//EMAC_DESCRIPTOR_T	*rx_desc;	/* point to virtual RX descriptor address*/
	EMAC_DESCRIPTOR_T	*tx_cur_desc;	/* point to current TX descriptor */
	EMAC_DESCRIPTOR_T	*rx_cur_desc;	/* point to current RX descriptor */
	EMAC_DESCRIPTOR_T   *tx_finished_desc;
	EMAC_DESCRIPTOR_T   *rx_finished_desc;
	unsigned long       cur_tx;
	unsigned int        cur_rx;	/* Index into the Rx buffer of next Rx pkt. */
	unsigned int        tx_flag;
	unsigned long       dirty_tx;
	// unsigned char       *tx_buf[TX_DESC_NUM];	/* Tx bounce buffers */
	dma_addr_t          tx_desc_dma; /* physical TX descriptor address */
	dma_addr_t          rx_desc_dma;	/* physical RX descriptor address */
	dma_addr_t          tx_bufs_dma; /* physical TX descriptor address */
	dma_addr_t          rx_bufs_dma; /* physical RX descriptor address */
#ifdef EMAC_STATISTICS
	unsigned long		rx_overrun;
	unsigned long		tx_underrun;
	unsigned long		tx_no_resource;
	unsigned long		rx_pkts;
	unsigned long		tx_pkts;
	unsigned long		interrupt_cnt;
	unsigned long		rx_intr_cnt;
	unsigned long		tx_intr_cnt;
#endif	
} EMAC_INFO_T;;


struct reg_ioctl_data {
    unsigned int    reg_addr;   /* the register address */
    unsigned int    val_in;     /* data write to the register */
    unsigned int    val_out;    /* data read from the register */
};

#define sl2312_eth_disable_interrupt()	REG32(SL2312_INTERRUPT_BASE + SL2312_IRQ_MASK) &= ~(1<<SL2312_INTERRUPT_EMAC)
#define sl2312_eth_enable_interrupt()	REG32(SL2312_INTERRUPT_BASE + SL2312_IRQ_MASK) |=  (1<<SL2312_INTERRUPT_EMAC)

#endif //_EMAC_SL2312_H