emac_sl2312.h

某个ARM9板子的实际bootloader 对裁剪

		unsigned int m_rx_pause_on	:  1;	/* received pause on frame interrupt mask */
		unsigned int m_cnt_full		:  1;	/* MIB counters half full interrupt mask */
		unsigned int m_tx_fail 		:  1;	/* Tx fail interrupt mask */
		unsigned int				:  6;
		unsigned int tx_underrun	:  1;	/* EMAC Tx FIFO underrun interrupt */
		unsigned int rx_overrun		:  1;   /* EMAC Rx FIFO overrun interrupt */
		unsigned int tx_pause_off	:  1;	/* received pause off frame interrupt */
		unsigned int rx_pause_off   :  1;	/* received pause off frame interrupt */
		unsigned int tx_pause_on	:  1;	/* transmit pause on frame interrupt */	 
		unsigned int rx_pause_on	:  1;	/* received pause on frame interrupt */
		unsigned int cnt_full		:  1;	/* MIB counters half full interrupt */
		unsigned int tx_fail		:  1; 	/* Tx fail interrupt */
		unsigned int 				: 10;
#endif
	} bits;
} EMAC_INT_MASK_T;		


/*******************************************/
/* the register structure of EMAC DMA      */
/*******************************************/
typedef union
{
	unsigned int bits32;
	struct bit2_ff00
	{
#if (BIG_ENDIAN==1) 	    
		unsigned int rp_wclk		:  4;	/* DMA_APB write clock period */
		unsigned int rp_rclk		:  4;	/* DMA_APB read clock period */
		unsigned int 				:  8;
		unsigned int device_id		: 12;
		unsigned int revision_id	:  4;
#else
		unsigned int revision_id	:  4;
		unsigned int device_id		: 12;
		unsigned int 				:  8;
		unsigned int rp_rclk		:  4;	/* DMA_APB read clock period */
		unsigned int rp_wclk		:  4;	/* DMA_APB write clock period */
#endif
	} bits;
} EMAC_DMA_DEVICE_ID_T;

typedef union
{
	unsigned int bits32;
	struct bit2_ff04
	{
#if (BIG_ENDIAN==1) 	    
		unsigned int ts_finish		:  1;	/* finished tx interrupt */
		unsigned int ts_derr		:  1;   /* AHB Bus Error while tx */ 
		unsigned int ts_perr		:  1;   /* Tx Descriptor protocol error */
		unsigned int ts_eodi		:  1;	/* TxDMA end of descriptor interrupt */
		unsigned int ts_eofi		:  1;   /* TxDMA end of frame interrupt */
		unsigned int rs_finish		:  1;   /* finished rx interrupt */
		unsigned int rs_derr		:  1;   /* AHB Bus Error while rx */ 
		unsigned int rs_perr		:  1;   /* Rx Descriptor protocol error */
		unsigned int rs_eodi		:  1;	/* RxDMA end of descriptor interrupt */
		unsigned int rs_eofi		:  1;	/* RxDMA end of frame interrupt */
		unsigned int tx_fail		:  1; 	/* Tx fail interrupt */
		unsigned int cnt_full		:  1;	/* MIB counters half full interrupt */
		unsigned int rx_pause_on	:  1;	/* received pause on frame interrupt */
		unsigned int tx_pause_on	:  1;	/* transmit pause on frame interrupt */	 
		unsigned int rx_pause_off   :  1;	/* received pause off frame interrupt */
		unsigned int tx_pause_off	:  1;	/* received pause off frame interrupt */
		unsigned int rx_overrun		:  1;   /* EMAC Rx FIFO overrun interrupt */
		unsigned int tx_underrun	:  1;	/* EMAC Tx FIFO underrun interrupt */
		unsigned int        		:  1;	/* write 1 to this bit will cause DMA HClk domain soft reset */
		unsigned int            	:  1;   /* write 1 to this bit will cause DMA PClk domain soft reset */
		unsigned int 				:  3;
		unsigned int loop_back		:  1;	/* loopback TxDMA to RxDMA */
		unsigned int m_tx_fail 		:  1;	/* Tx fail interrupt mask */
		unsigned int m_cnt_full		:  1;	/* MIB counters half full interrupt mask */
		unsigned int m_rx_pause_on	:  1;	/* received pause on frame interrupt mask */
		unsigned int m_tx_pause_on  :  1;	/* transmit pause on frame interrupt mask */
		unsigned int m_rx_pause_off :  1;	/* received pause off frame interrupt mask */
		unsigned int m_tx_pause_off	:  1;	/* received pause off frame interrupt mask */
		unsigned int m_rx_overrun	:  1;   /* EMAC Rx FIFO overrun interrupt mask */
		unsigned int m_tx_underrun	:  1;	/* EMAC Tx FIFO underrun interrupt mask */
#else
		unsigned int m_tx_underrun	:  1;	/* EMAC Tx FIFO underrun interrupt mask */
		unsigned int m_rx_overrun	:  1;   /* EMAC Rx FIFO overrun interrupt mask */
		unsigned int m_tx_pause_off	:  1;	/* received pause off frame interrupt mask */
		unsigned int m_rx_pause_off :  1;	/* received pause off frame interrupt mask */
		unsigned int m_tx_pause_on  :  1;	/* transmit pause on frame interrupt mask */
		unsigned int m_rx_pause_on	:  1;	/* received pause on frame interrupt mask */
		unsigned int m_cnt_full		:  1;	/* MIB counters half full interrupt mask */
		unsigned int m_tx_fail 		:  1;	/* Tx fail interrupt mask */
		unsigned int loop_back		:  1;	/* loopback TxDMA to RxDMA */
		unsigned int 				:  3;
		unsigned int            	:  1;   /* write 1 to this bit will cause DMA PClk domain soft reset */
		unsigned int        		:  1;	/* write 1 to this bit will cause DMA HClk domain soft reset */
		unsigned int tx_underrun	:  1;	/* EMAC Tx FIFO underrun interrupt */
		unsigned int rx_overrun		:  1;   /* EMAC Rx FIFO overrun interrupt */
		unsigned int tx_pause_off	:  1;	/* received pause off frame interrupt */
		unsigned int rx_pause_off   :  1;	/* received pause off frame interrupt */
		unsigned int tx_pause_on	:  1;	/* transmit pause on frame interrupt */	 
		unsigned int rx_pause_on	:  1;	/* received pause on frame interrupt */
		unsigned int cnt_full		:  1;	/* MIB counters half full interrupt */
		unsigned int tx_fail		:  1; 	/* Tx fail interrupt */
		unsigned int rs_eofi		:  1;	/* RxDMA end of frame interrupt */
		unsigned int rs_eodi		:  1;	/* RxDMA end of descriptor interrupt */
		unsigned int rs_perr		:  1;   /* Rx Descriptor protocol error */
		unsigned int rs_derr		:  1;   /* AHB Bus Error while rx */ 
		unsigned int rs_finish		:  1;   /* finished rx interrupt */
		unsigned int ts_eofi		:  1;   /* TxDMA end of frame interrupt */
		unsigned int ts_eodi		:  1;	/* TxDMA end of descriptor interrupt */
		unsigned int ts_perr		:  1;   /* Tx Descriptor protocol error */
		unsigned int ts_derr		:  1;   /* AHB Bus Error while tx */ 
		unsigned int ts_finish		:  1;	/* finished tx interrupt */
#endif
	} bits;
} EMAC_DMA_STATUS_T;

typedef union
{
	unsigned int bits32;
	struct bit2_ff08
	{
#if (BIG_ENDIAN==1) 	    
		unsigned int td_start		:  1;	/* Start DMA transfer */
		unsigned int td_continue	:  1;   /* Continue DMA operation */
		unsigned int td_chain_mode	:  1;	/* Descriptor Chain Mode;1-Descriptor Chain mode, 0-Direct DMA mode*/
		unsigned int 				:  2;
		unsigned int td_prot		:  4;	/* TxDMA protection control */
		unsigned int td_burst_size  :  2;	/* TxDMA max burst size for every AHB request */
		unsigned int td_bus		    :  1;	/* peripheral bus width;0 - 8 bits;1 - 16 bits */
		unsigned int td_endian		:  1;	/* AHB Endian. 0-little endian; 1-big endian */
		unsigned int td_finish_en   :  1;	/* DMA Finish Event Interrupt Enable;1-enable;0-mask */
		unsigned int td_fail_en 	:  1;	/* DMA Fail Interrupt Enable;1-enable;0-mask */
		unsigned int td_perr_en 	:  1;	/* Protocol Failure Interrupt Enable;1-enable;0-mask */
		unsigned int td_eod_en  	:  1;	/* End of Descriptor interrupt Enable;1-enable;0-mask */
		unsigned int td_eof_en      :  1;   /* End of frame interrupt Enable;1-enable;0-mask */
		unsigned int 				: 14;
#else
		unsigned int 				: 14;
		unsigned int td_eof_en      :  1;   /* End of frame interrupt Enable;1-enable;0-mask */
		unsigned int td_eod_en  	:  1;	/* End of Descriptor interrupt Enable;1-enable;0-mask */
		unsigned int td_perr_en 	:  1;	/* Protocol Failure Interrupt Enable;1-enable;0-mask */
		unsigned int td_fail_en 	:  1;	/* DMA Fail Interrupt Enable;1-enable;0-mask */
		unsigned int td_finish_en   :  1;	/* DMA Finish Event Interrupt Enable;1-enable;0-mask */
		unsigned int td_endian		:  1;	/* AHB Endian. 0-little endian; 1-big endian */
		unsigned int td_bus		    :  1;	/* peripheral bus width;0 - 8 bits;1 - 16 bits */
		unsigned int td_burst_size  :  2;	/* TxDMA max burst size for every AHB request */
		unsigned int td_prot		:  4;	/* TxDMA protection control */
		unsigned int 				:  2;
		unsigned int td_chain_mode	:  1;	/* Descriptor Chain Mode;1-Descriptor Chain mode, 0-Direct DMA mode*/
		unsigned int td_continue	:  1;   /* Continue DMA operation */
		unsigned int td_start		:  1;	/* Start DMA transfer */
#endif
	} bits;
} EMAC_TXDMA_CTRL_T;
				
typedef union 
{
	unsigned int bits32;
	struct bit2_ff0c
	{
#if (BIG_ENDIAN==1) 	    
		unsigned int td_first_des_ptr	: 28;/* first descriptor address */
		unsigned int td_busy			:  1;/* 1-TxDMA busy; 0-TxDMA idle */
		unsigned int 					:  3;
#else
		unsigned int 					:  3;
		unsigned int td_busy			:  1;/* 1-TxDMA busy; 0-TxDMA idle */
		unsigned int td_first_des_ptr	: 28;/* first descriptor address */
#endif
	} bits;
} EMAC_TXDMA_FIRST_DESC_T;					

typedef union
{
	unsigned int bits32;
	struct bit2_ff10
	{
#if (BIG_ENDIAN==1) 	    
		unsigned int ndar			: 28;	/* next descriptor address */
		unsigned int eofie			:  1;	/* end of frame interrupt enable */
		unsigned int dec			:  1;	/* AHB bus address increment(0)/decrement(1) */
		unsigned int sof_eof		:  2;
#else
		unsigned int sof_eof		:  2;
		unsigned int dec			:  1;	/* AHB bus address increment(0)/decrement(1) */
		unsigned int eofie			:  1;	/* end of frame interrupt enable */
		unsigned int ndar			: 28;	/* next descriptor address */
#endif
	} bits;
} EMAC_TXDMA_CURR_DESC_T;
			

typedef union
{
	unsigned int bits32;
	struct bit2_ff14
	{
#if (BIG_ENDIAN==1) 	    
		unsigned int rd_start		:  1;	/* Start DMA transfer */
		unsigned int rd_continue	:  1;   /* Continue DMA operation */
		unsigned int rd_chain_mode	:  1;	/* Descriptor Chain Mode;1-Descriptor Chain mode, 0-Direct DMA mode*/
		unsigned int 				:  2;
		unsigned int rd_prot		:  4;	/* DMA protection control */
		unsigned int rd_burst_size  :  2;	/* DMA max burst size for every AHB request */
		unsigned int rd_bus		    :  1;	/* peripheral bus width;0 - 8 bits;1 - 16 bits */
		unsigned int rd_endian		:  1;	/* AHB Endian. 0-little endian; 1-big endian */
		unsigned int rd_finish_en   :  1;	/* DMA Finish Event Interrupt Enable;1-enable;0-mask */
		unsigned int rd_fail_en  	:  1;	/* DMA Fail Interrupt Enable;1-enable;0-mask */
		unsigned int rd_perr_en 	:  1;	/* Protocol Failure Interrupt Enable;1-enable;0-mask */
		unsigned int rd_eod_en  	:  1;	/* End of Descriptor interrupt Enable;1-enable;0-mask */
		unsigned int rd_eof_en      :  1;   /* End of frame interrupt Enable;1-enable;0-mask */
		unsigned int 				: 14;
#else
		unsigned int 				: 14;
		unsigned int rd_eof_en      :  1;   /* End of frame interrupt Enable;1-enable;0-mask */
		unsigned int rd_eod_en  	:  1;	/* End of Descriptor interrupt Enable;1-enable;0-mask */
		unsigned int rd_perr_en 	:  1;	/* Protocol Failure Interrupt Enable;1-enable;0-mask */
		unsigned int rd_fail_en  	:  1;	/* DMA Fail Interrupt Enable;1-enable;0-mask */
		unsigned int rd_finish_en   :  1;	/* DMA Finish Event Interrupt Enable;1-enable;0-mask */
		unsigned int rd_endian		:  1;	/* AHB Endian. 0-little endian; 1-big endian */
		unsigned int rd_bus		    :  1;	/* peripheral bus width;0 - 8 bits;1 - 16 bits */
		unsigned int rd_burst_size  :  2;	/* DMA max burst size for every AHB request */
		unsigned int rd_prot		:  4;	/* DMA protection control */
		unsigned int 				:  2;
		unsigned int rd_chain_mode	:  1;	/* Descriptor Chain Mode;1-Descriptor Chain mode, 0-Direct DMA mode*/
		unsigned int rd_continue	:  1;   /* Continue DMA operation */
		unsigned int rd_start		:  1;	/* Start DMA transfer */
#endif
	} bits;
} EMAC_RXDMA_CTRL_T;
				
typedef union 
{
	unsigned int bits32;
	struct bit2_ff18
	{
#if (BIG_ENDIAN==1) 	    
		unsigned int rd_first_des_ptr	: 28;/* first descriptor address */
		unsigned int rd_busy			:  1;/* 1-RxDMA busy; 0-RxDMA idle */
		unsigned int 					:  3;
#else
		unsigned int 					:  3;
		unsigned int rd_busy			:  1;/* 1-RxDMA busy; 0-RxDMA idle */
		unsigned int rd_first_des_ptr	: 28;/* first descriptor address */
#endif
	} bits;
} EMAC_RXDMA_FIRST_DESC_T;					

typedef union
{
	unsigned int bits32;
	struct bit2_ff1c
	{
#if (BIG_ENDIAN==1) 	    
		unsigned int ndar			: 28;	/* next descriptor address */
		unsigned int eofie			:  1;	/* end of frame interrupt enable */
		unsigned int dec			:  1;	/* AHB bus address increment(0)/decrement(1) */
		unsigned int sof_eof		:  2;
#else
		unsigned int sof_eof		:  2;
		unsigned int dec			:  1;	/* AHB bus address increment(0)/decrement(1) */
		unsigned int eofie			:  1;	/* end of frame interrupt enable */
		unsigned int ndar			: 28;	/* next descriptor address */
#endif
	} bits;
} EMAC_RXDMA_CURR_DESC_T;


/********************************************/
/*          Descriptor Format               */
/********************************************/
typedef union frame_control_u
	{
		unsigned int bits32;
		struct bd_bits_0000
		{
#if (BIG_ENDIAN==1) 	    
			unsigned int own 		: 1;	/* owner bit. 0-CPU, 1-DMA */
			unsigned int derr		: 1;	/* data error during processing this descriptor */
			unsigned int perr		: 1;	/* protocol error during processing this descriptor */
			unsigned int            : 1;
			unsigned int vlan_tag   : 1;    /* 802.1q vlan tag packet */
			unsigned int mcast_frame: 1;	/* received frame is multicast frame */
			unsigned int bcast_frame: 1;	/* received frame is broadcast frame */
			unsigned int ucast_mac1 : 1;	/* received frame is unicast frame of MAC address 1 */
			unsigned int ucast_mac2 : 1;	/* received frame is unicast frame of MAC address 2 */
			unsigned int frame_state: 3;    /* reference Rx Status1 */
			unsigned int desc_count : 4;	/* number of descriptors used for the current frame */
			unsigned int buffer_size:16;	/* transfer buffer size associated with current description*/
#else