flash_nand.c

某个ARM9板子的实际bootloader 对裁剪

		for(j=0;j<info_flash[6];j++)		// Read OOB
		{
			//hal_delay_us(5);
			dev_oob[j] = *adr++;
		}
		*/
	}

	for(j=0;j<info_flash[6];j++)		// Read OOB
	{
			dev_oob[j] = page_data[info_flash[5]+j];
	}
	
	// Waiting ECC generation completey
	opcode=FLASH_CTRL_READ_REG(NFLASH_ECC_STATUS);
	while(!(opcode&0x80000000)) //polling flash access 31b
	{
		opcode=FLASH_CTRL_READ_REG(NFLASH_ECC_STATUS);
		flash_delay();
	}
	
	for(j=0;j<(info_flash[5]/512);j++)
	{//for 512 bytes ~ 2k page
	
		//opcode = 0x00000000|dev_oob[info_flash[6]-3-3*j]<<16|dev_oob[info_flash[6]-2-3*j]<<8|dev_oob[info_flash[6]-1-3*j];
		//opcode = (dev_oob[j*16+13] << 16)|(dev_oob[j*16+14] << 8)|(dev_oob[j*16+15]);
		opcode = 0x00000000|dev_oob[info_flash[6]-3-4*j]<<16|dev_oob[info_flash[6]-2-4*j]<<8|dev_oob[info_flash[6]-1-4*j];		    
		
		//opcode=FLASH_CTRL_READ_REG(NFLASH_ECC_CODE_GEN0+(j*4));
	
		FLASH_CTRL_WRITE_REG(NFLASH_ECC_OOB, opcode);
		opcode = 0x00000000|(j<<8); //select ECC code generation 0
		FLASH_CTRL_WRITE_REG(NFLASH_ECC_CONTROL, opcode); //???
	
		opcode=FLASH_CTRL_READ_REG(NFLASH_ECC_STATUS);
		
		ndirect = 0x4000;
		nmode = 1 ;
		if((opcode&0x00000003)==0x03)		// un-correctable
		{
			printf("\nPageRead Uncorrectable error !!\n");
			return FAIL;
		}
		else if((opcode&0x00000003)==0x01)	// 1-bit data error
		{
			ecc_byte = (opcode|0x0000ff80)>>7;
			ecc_bit = (opcode|0x00000078)>>3;
			printf("\nPageRead One bit data error !!\n");
			printf("Correct bit%x of byte%x\n",ecc_bit,ecc_byte);
			ecc = page_data[j*512+ecc_byte];
			ecc ^= (1<<ecc_bit);
			page_data[j*512+ecc_byte] = ecc;
		}
		else if((opcode&0x00000003)==0x02)	// 1-bit ecc error
		{
			printf("\nPageRead One bit ECC error !!\n");
			printf("Ecc comparison error bit : %x \n",(opcode|0x00000038));
			return FAIL;
	
		}
		else if((opcode&0x00000003)==0x00)	// no error
		{
			return PASS;
		}
	
	}
	
	return PASS;

}

int pagewrite(void* addr, void* data, int len)
{
	UINT32 i,j,tt,nwidth,err_flag=PASS;
	UINT32 page_add = (UINT32*)addr;
	UINT8  *adr=addr,ecc_buf[3],oob[64];
	UINT8  *write_data = (UINT8*)data ;
	
	nwidth = NFLASH_WiDTH8;
	
	//ndirect = 0;
	//	nmode = 1 ;
	ndirect = 0x4000;
		nmode = 1 ;	
		

	memset(oob, 0xff, info_flash[6]);	
		
	ADD5=ADD4=ADD3=ADD2=0;
	if(info_flash[5] < 528)
	{
		ADD5=(UINT32)(((UINT64)page_add<<8)>>32);
		ADD4=(UINT32)(((UINT64)page_add<<16)>>32);
		ADD3=(UINT32)(((UINT64)page_add<<24)>>32);
		ADD2=(UINT32)(((UINT64)page_add<<32)>>32);
	}
	else
	{
		ADD5=(UINT32)(((UINT64)page_add<<16)>>32);
		ADD4=(UINT32)(((UINT64)page_add<<24)>>32);
		ADD3=(UINT32)(((UINT64)page_add<<32)>>32);
	
	}
	
	if(nmode == 2)
	{
		FLASH_CTRL_WRITE_REG(NFLASH_FIFO_CONTROL, 0x8000); //clear fifo
		FLASH_WRITE_DMA_REG(DMA_MAIN_CFG, 0x1); //enable DMA
		FLASH_WRITE_DMA_REG(DMA_CH0_SRC_ADDR, (UINT32)write_data); //src_address
		FLASH_WRITE_DMA_REG(DMA_CH0_DST_ADDR, 0x65888800); //dest_address
		FLASH_WRITE_DMA_REG(DMA_CH0_LLP, 0x0); //LLP
		FLASH_WRITE_DMA_REG(DMA_CH0_SIZE, (info_flash[5]/4)); //size 32bit DMA
		FLASH_WRITE_DMA_REG(DMA_CH0_CFG, 0x2); //CFG
		FLASH_WRITE_DMA_REG(DMA_CH0_CSR, 0x11295); //CSR
	
	}
	
	//reset(chip0_en);
	//make8_ecc_512(ecc_buf,write_data);
	//EccGen(write_data);
	//FLASH_CTRL_WRITE_REG(NFLASH_ECC_CONTROL, 0x00000000); //set 31b = 0
	FLASH_CTRL_WRITE_REG(NFLASH_ECC_CONTROL, 0x80000003); //set 31b = 0 & ECC pause enable & Ecc clear
	
	
	if(ndirect==0x0)
	{
	
		if(info_flash[1]<64)
		{
	
			FLASH_CTRL_WRITE_REG(NFLASH_COUNT, 0x0f01ff22); //set only command & address and two data
			opcode = 0x00108000;
			//opcode = 0x00001080;
		}
		if(info_flash[1]>=64&&info_flash[1]<256)
		{
			FLASH_CTRL_WRITE_REG(NFLASH_COUNT, 0x3f07ff31); //set only command & address and two data
			opcode = 0x00001080;
		}
		if(info_flash[1]>256)
		{
			FLASH_CTRL_WRITE_REG(NFLASH_COUNT, 0x3f07ff41); //set only command & address and two data
			opcode = 0x00001080;
		}
		opcode |= (ADD5<<24);
		FLASH_CTRL_WRITE_REG(NFLASH_COMMAND_ADDRESS, opcode); //write address 0x00
	
		opcode = 0x00000000|(ADD4<<24)|(ADD3<<16)|(ADD2<<8);
		FLASH_CTRL_WRITE_REG(NFLASH_ADDRESS, opcode); //write address 0x00
	
		if(nmode == 1) //indirect mode
		{
			for(i=0;i<info_flash[5];i++)
			{
				tt = write_data[i];
				////////
				if((i&0x03)==0x01)
				tt<<=8;
				else if((i&0x03)==0x02)
				tt<<=16;
				else if((i&0x03)==0x03)
				tt<<=24;
	
				//FLASH_CTRL_WRITE_REG(NFLASH_DATA, write_data[i]); //write address 0x00
				FLASH_CTRL_WRITE_REG(NFLASH_DATA, tt); //write address 0x00
				opcode = 0x80003000|chip0_en|nwidth|ndirect; //set start bit & 8bits read command
				FLASH_CTRL_WRITE_REG(NFLASH_ACCESS, opcode);
	
				while(opcode&0x80000000) //polling flash access 31b
				{
					opcode=FLASH_CTRL_READ_REG(NFLASH_ACCESS);
					flash_delay();
				}
			}
		}
		else if(nmode == 2) ////DMA mode
		{
			//opcode=FLASH_CTRL_READ_REG(NFLASH_FIFO_ADDRESS);
			//opcode = opcode>>8;
			opcode = 0x00888800;
			FLASH_CTRL_WRITE_REG(NFLASH_FIFO_ADDRESS, opcode);
	
			FLASH_CTRL_WRITE_REG(NFLASH_FIFO_CONTROL, 0x80003000);
			//opcode=FLASH_CTRL_READ_REG(NFLASH_FIFO_CONTROL);
			//	while(opcode&0x80000000) //polling flash access 31b
			//	{
			//	  opcode=FLASH_CTRL_READ_REG(NFLASH_FIFO_CONTROL);
			//	  flash_delay();
			//	}
			//DMA TC int status Rg
			opcode=FLASH_READ_DMA_REG(DMA_TC);
			while(!(opcode&0x01)) //polling flash access 31b
			{
				opcode=FLASH_READ_DMA_REG(DMA_TC);
				flash_delay();
			}
			//Disable channel 0 DMA
			FLASH_WRITE_DMA_REG(DMA_CH0_CSR, 0x0);
	
			//write clear int
			FLASH_WRITE_DMA_REG(DMA_INT_TC_CLR, 0x1);
		}
	
		///////////////
		opcode=FLASH_CTRL_READ_REG(NFLASH_ECC_STATUS);
		while(!(opcode&0x80000000)) //polling flash access 31b
		{
			opcode=FLASH_CTRL_READ_REG(NFLASH_ECC_STATUS);
			flash_delay();
		}
	
		for(i=0;i<info_flash[6];i++)
			oob[i]=0xff;
	
		for(i=0;i<(info_flash[5]/512);i++)
		{
			opcode=FLASH_CTRL_READ_REG(NFLASH_ECC_CODE_GEN0+(i*4));
	
			/*			make8_ecc_512(ecc_buf,write_data);  ecc_cmp
	
			for(j=0;j<info_flash[5];j++)
			ck_buf[j] = write_data[j+(i*512)];
	
			//      	make8_ecc_512(ecc_buf,ck_buf);
			ecc_cmp = (ecc_buf[2]<<16)|(ecc_buf[1]<<8)|ecc_buf[0];
			if(opcode != ecc_cmp)
			printf("\n***  ECC_Generation(8) %d error H/W : %x  S/W : %x   ***\n",i,opcode,ecc_cmp);
			*/
			for(j=3;j>0;j--)
			oob[info_flash[6]-j-(i*3)] = (opcode<<((4-j)*8)) >>24;
	
			ecc_cmp=0x0;
		}
	
	
		//disable ecc
		FLASH_CTRL_WRITE_REG(NFLASH_ECC_CONTROL, 0x00000000);
		if(nmode == 1) //indirect mode
		{
			for(i=0;i<info_flash[6];i++)
			{
				tt = oob[i];
				////////
				if((i&0x03)==0x01)
				tt<<=8;
				else if((i&0x03)==0x02)
				tt<<=16;
				else if((i&0x03)==0x03)
				tt<<=24;
				////////
	
				//FLASH_CTRL_WRITE_REG(NFLASH_DATA, write_data[i]); //write address 0x00
				FLASH_CTRL_WRITE_REG(NFLASH_DATA, tt); //write address 0x00
				opcode = 0x80003000|chip0_en|nwidth|ndirect; //set start bit & 8bits read command
				FLASH_CTRL_WRITE_REG(NFLASH_ACCESS, opcode);
	
				while(opcode&0x80000000) //polling flash access 31b
				{
					opcode=FLASH_CTRL_READ_REG(NFLASH_ACCESS);
					flash_delay();
				}
			}
			////////////////
	
			err_flag=StatusCheck(chip0_en, def_width);
			if (err_flag !=PASS){
				printf("PageWrite : Invalid Blocks are detected while Real Time Mapping(ADD= %x %x %x %x)\n",ADD5,ADD4,ADD3,ADD2);
				if(info_flash[1]<=8)	ADD2&=0xf0;     // In case of 1MB, 2MB, 4MB, 8MB
				else			ADD2&=0xe0;     //In case of 16MB, 32MB,64MB,128MB
				page_add=(UINT64)((ADD5<<24)+(ADD4<<16)+(ADD3<<8)+ADD2);
				//				RealTimeBadMark(page_add, chip0_en);
				return FAIL;
			}
		}
		else if(nmode == 2) ////DMA mode
		{
			FLASH_CTRL_WRITE_REG(NFLASH_FIFO_CONTROL, 0x8000); //clear fifo
			FLASH_WRITE_DMA_REG(DMA_CH0_SRC_ADDR, (UINT32)(write_data+info_flash[5])); //src_address
			FLASH_WRITE_DMA_REG(DMA_CH0_DST_ADDR, 0x65888800); //dest_address
			FLASH_WRITE_DMA_REG(DMA_CH0_LLP, 0x0); //LLP
			FLASH_WRITE_DMA_REG(DMA_CH0_SIZE, (info_flash[6]/4)); //size
			FLASH_WRITE_DMA_REG(DMA_CH0_CSR, 0x11295); //CSR
	
			opcode = 0x00888800;
			FLASH_CTRL_WRITE_REG(NFLASH_FIFO_ADDRESS, opcode);
	
			FLASH_CTRL_WRITE_REG(NFLASH_FIFO_CONTROL, 0x80003000);
			opcode=FLASH_CTRL_READ_REG(NFLASH_FIFO_CONTROL);
			while(opcode&0x80000000) //polling flash access 31b
			{
				opcode=FLASH_CTRL_READ_REG(NFLASH_FIFO_CONTROL);
				flash_delay();
			}
			//Flash status Reg
			//write clear fifo_int
			FLASH_CTRL_WRITE_REG(FLASH_STATUS, 0x20000);
			err_flag = PASS;
		}
	
	}
	else   //direct mode
	{
		FLASH_CTRL_WRITE_REG(NFLASH_ACCESS, NFLASH_DIRECT);
		//memcpy(adr, write_data, info_flash[5]);
		
		for(i=0;i<info_flash[5];i++)
		{
			//hal_delay_us(5);
			//			adr = (UINT8 *)(SL2312_FLASH_SHADOW + page_add * info_flash[5] + i);
			*adr++ = write_data[i] ;
	
		}
		
		///////////////
		opcode=FLASH_CTRL_READ_REG(NFLASH_ECC_STATUS);
		while(!(opcode&0x80000000)) //polling flash access 31b
		{
			opcode=FLASH_CTRL_READ_REG(NFLASH_ECC_STATUS);
			flash_delay();
		}
	
	
		for(i=0;i<(info_flash[5]/512);i++)
		{
			opcode=FLASH_CTRL_READ_REG(NFLASH_ECC_CODE_GEN0+(i*4));
	
			////////////////////////////
			//for(j=4;j>0;j--)
    		//     oob[(info_flash[6]-j-(i*4))] = 0x0;
    		      
			for(j=3;j>0;j--)
    		      oob[(info_flash[6]-j-(i*4))] = (opcode<<((4-j)*8)) >>24;
    		
			////////////////////////////
			
		}
	
		//disable ecc
		FLASH_CTRL_WRITE_REG(NFLASH_ECC_CONTROL, 0x00000000);
	
		//memcpy((adr+info_flash[5]), oob, info_flash[5]);
		
		for(i=0;i<info_flash[6];i++)
		{
			//hal_delay_us(5);
			//		 	adr = (UINT8 *)(SL2312_FLASH_SHADOW + page_add * info_flash[5] + i);
			*adr++ = oob[i] ;
		}
		
	
		err_flag = PASS;
	}
	
	
	//printf("****************** Entered Data(1page)***************\n");
	//for(i=0;i<info_flash[4];i++)
	//{
	//	if(i%32==0)
	//	    printf("\n%02x",*(write_data+i));
	//	else
	//		printf("%02x",*(write_data+i));
	//}
	//printf("\n*****************************************************************\n\n");
	
	//	PageRead(page_data,page_add, chip0_en);
	/*
	for(i=0;i<info_flash[5];i++){
	if(*(write_data+i)!=*(page_data+i)){
	err_flag=FAIL;
	break;
	}
	}
	if(err_flag!=PASS){
	printf("PageWrite_R : Invalid Blocks are detected while Real Time Mapping(ADD= %x %x %x)!!\n",ADD4,ADD3,ADD2);
	if(info_flash[1]<=8)	ADD2&=0xf0;     // In case of 1MB, 2MB, 4MB, 8MB
	else			ADD2&=0xe0;     //In case of 16MB, 32MB,64MB,128MB
	page_add=(UINT64)((ADD5<<24)+(ADD4<<16)+(ADD3<<8)+ADD2);
	RealTimeBadMark(page_add, chip0_en);
	return FAIL;
	}
	*/
	return PASS;
	

}
//#endif // CYGONCE_DEVS_FLASH_TOSHIBA_TC58XXX_INL

// EOF flash_tc58xxx.inl
//#endif // FLASH_TYPE_NAND