option.inc

S3C2440开发板SD驱动程序。ADS1.2源码

;===========================================
; NAME: OPTION.INC
; DESC: Configuration options for .S files
; HISTORY:
; 02.28.2002: ver 0.0
; 03.11.2003: ver 0.0	attached for 2440.
;===========================================

;Start address of each stacks

_STACK_BASEADDRESS	EQU 0x33ff8000
_MMUTT_STARTADDRESS	EQU 0x33ff8000
_ISR_STARTADDRESS	EQU 0x33ffff00

		GBLL 	PLL_ON_START
PLL_ON_START	SETL 	{FALSE}

		GBLL	ENDIAN_CHANGE
ENDIAN_CHANGE	SETL	{FALSE}

		GBLA	ENTRY_BUS_WIDTH
ENTRY_BUS_WIDTH	SETA	16


;BUSWIDTH = 16,32
		GBLA    BUSWIDTH	;max. bus width for the GPIO configuration
BUSWIDTH	SETA    32

;When xtal=16.9344MHz
		GBLA	XTAL_SEL
XTAL_SEL	SETA	16934400

		GBLA	FCLK
FCLK		SETA	296352000

		GBLA	UCLK
UCLK		SETA	48000000

CLKDIV_VAL	EQU	1	; 0=1:1:1, 1=1:1:2, 2=1:2:2, 3=1:2:4, 4=1:4:4, 5=1:4:8, 6=1:3:3, 7=1:3:6
    	
 [ XTAL_SEL = 12000000
    	[ FCLK = 101606000
M_MDIV		EQU	246		;Fin=12.0MHz Fout=101.606MHz
M_PDIV		EQU	13
M_SDIV		EQU	1
    	]

    	[ FCLK = 203200000
M_MDIV		EQU	246		;Fin=12.0MHz Fout=203.2MHz
M_PDIV		EQU	13
M_SDIV		EQU	0
    	]
    	
    	[ UCLK = 48000000
U_MDIV		EQU	56		;Fin=12.0MHz Fout=48MHz
U_PDIV		EQU	2
U_SDIV		EQU	2
    	]

    	[ UCLK = 96000000
U_MDIV		EQU	56		;Fin=12.0MHz Fout=96MHz
U_PDIV		EQU	2
U_SDIV		EQU	1
    	]    	

  |; else if XTAL_SEL = 16.9344Mhz

    	[ FCLK = 296352000
M_MDIV		EQU	246	;Fin=16.93MHz Fout=296MHz
M_PDIV		EQU	13
M_SDIV		EQU	0
    	]
    
	[ UCLK = 48000000
U_MDIV		EQU	60	;Fin=16.93MHz Fout=48MHz
U_PDIV		EQU	4
U_SDIV		EQU	2
	]
	
	[ UCLK = 96000000
U_MDIV		EQU	60	;Fin=16.93MHz Fout=96MHz
U_PDIV		EQU	4
U_SDIV		EQU	1
	]    
 
 ]; end of if XTAL_SEL = 12000000.
 
 
	END