ibmlpt.txt

Parallel Port description of the communication port

This latter may be a problem after booting or rebooting.  One approach
is to use current limiting resistors in series "just in case".  You should
ideally still have pullup resistors too.  (The 1K value is chosen for LS TTL,
to keep the 2.4 V output at no more than 2.4 mA sourcing).

                         1K            4.7K
         Dn Out --------^^^^^-----+----^^^^^------ (+5v)
                                  |
                                Switch
                                  |
         Ground ------------------+--------------- (Gnd)


20. Optocoupled inputs

To be written.

21. Matrix scanning

In an upcoming project, I want to use a 4x4 keypad as an input.  In this
type of keypad (warning: there are other types), each key makes a connection
from one row to one column, when pressed.  My first design has the "columns"
connected to the 4 Control Out pins, while the "rows" are connected to 4 of
the Status Inputs.  Normally, all 4 control outputs were programmed high,
but to scan the keypad, I would lower one control output at a time, and
read the 4 status inputs at that time.  The 4 status inputs are each
pulled high to +5 volts via a 10K resistor, or left to float.  (Use Dn
plus resistors rather than +5 external supply?)  This scheme could be
expanded to as large as 4x5 (4 Cn outputs, 5 Sn inputs).

                              10 K
     S4 ------------X X X X--^^^^^--+--- (+5)
     S5 ------------X X X X--^^^^^--+
     S6 ------------X X X X--^^^^^--+     (these pullups optional?)
     S7 ------------X X X X--^^^^^--+
                    | | | |
     C3 ------------+ | | |      Scan one Cn low at a time, read Sn each time
     C2 --------------+ | |
     C1 ----------------+ |
     C0 ------------------+


Alternate scheme.  Use Dn's for scanning output rows, through diodes which
will isolate them from each other if two keys in the same column are pressed.
(Otherwise we have drivers fighting, and indeterminate voltage levels).
Germanium small signal diodes have less voltage drop.  Use the Cn pins
as inputs (with existing pullups) - program Control Out for high TTL levels,
and read the feedback register for input (counting inversions).  No extra
power supply is needed.  The diode between TTL output low and TTL input low
will push the TTL noise margins, but you can usually get by with it.  This
scheme could be expanded up to 8x4 (8 Dn outputs, 4 Cn used as inputs).  If
we know that only one key (or one key per column) will be pressed at a time,
the diodes can be omitted.

           1N914
     D0 ----|<|-----X X X X      (Set all Cn high),
     D1 ----|<|-----X X X X      Scan one Dn low at a time, read all Cn
     D2 ----|<|-----X X X X
     D3 ----|<|-----X X X X
                    | | | |
     C3 ------------+ | | |
     C2 --------------+ | |
     C1 ----------------+ |
     C0 ------------------+

Note that if we press three switches in the matrix which form 3 corners of
a box, it will appear as if all 4 corners are pressed; this is true of any
such matrix, unless each switch has its own diode.

I hope to have some results to share in a later revision of this doc.

22. Tutorial on TTL outputs

In response to requests, here is a brief tutorial on chip outputs.  As a
preface, it is conventional to discuss current as flowing from positive to
negative, even though we know full well that electrons actually move in the
opposite directions; it's just a convention, not ignorance.

         +5                                         +5
        /                                            \
    ---H                                             /   external resistor
        \                                            \
         |_____                           ___________/
         |   out                          |   out
        /                                /
    ---L                             ---L
        \                                \
        Gnd                              Gnd

    Totem Pole                       Open Collector


Regular TTL outputs basically consist of a two "stacked" transistor in series
between +5 volts and ground, with the output coming from the connection between

them.  This is called a "totem pole output".  At any given time one of these
transistors is conducting and the other is not.  To pull the output "high",
the transistor from +5 to the output conducts (H), which "sources" positive
current from the output to ground (that is, an external device between the
output and ground will get power).  To pull the output low, only the lower
transistor (L) conducts, "sinking" current to ground; an external device
between +5 volts and the output can be energized.  Current flows into the
chip for low, out of it for high.

         +5
        /    |
    ---H on  V
        \      -->
         |________        TTL output on = 1 = high, "sourcing" current
         |   out  \
        /         / |
    ---L off      \ V
        \_________/
        Gnd


       +5_________
        /         \
    ---H off      / |
        \         \ V
         |________/      TTL output off = 0 = low, "sinking" current
         |  <-- out
        /
    ---L on |
        \   V
        Gnd

The 0 / pull low current capacity (sinking) is larger than the 1 / pull high
capacity (sourcing).  If you want to drive something like an LED, or a solid
state relay, you can get more current from the TTL outputs by connecting it
between +5 and the gate output (second picture) - *if* it's electrically
isolated from ground.  You still have to check the current and voltage
ratings, tho.

One key here is that the chip is always trying to pull either high
or low, and the currently conducting transistor has voltage and current
limits, beyond which it can be damaged.  It is not good design to connect
two such outputs which may have different states - one pulling high and one
low - because this will exceed the current specs.  However, if you do, the
one pulling low will "win", since TTL can sink (pull low) more strongly
than it can source (pull high).  And there is some slack in the specs, so
this does not always immediately damage the chip; we'll get back to this.
These are the type of outputs on the DATA lines on the original IBM
parallel port.  (Well, not exactly, but I'll get back to that too).

Another type of output is the "open collector".  In this case, there is a
transistor from the output pin to ground, but none to +5 volts.  The two
states are 0, "conducting to ground" (pulling low), and 1, "not conducting"
(floating, not pulled either way).  Externally, you can connect a resistor
of proper value between the line and +5 volts to pull the line high when
the chip output is floating.  The value is chosen such that when the output
is conducting to ground, it overpowers the external resistor and the line
goes low.  The advantage of this scheme is that you can connect multiple
open collector outputs together (or even slip in one totem pole).  Every
output that is floating is ignored (and the resistor will pull the line
high if and only if all outputs are floating); multiple outputs pulling
low cause no conflict.  This is the type of output used for CONTROL lines
in the original IBM parallel port.

Since each parallel port control output line has a corresponding feedback
bit that can be read (mainly for diagnostics, to see if the line really goes
high or low), it is possible to program these CONTROL outputs "high" (really
floating), and then allow external signals control the high or low state
of the line.  An external open collector output, or a totem pole one, is
capable of pulling the line high (reinforcing the pullup resistor) or low
(overpowring it) without exceeding current specs.  In this way you can use
the control lines as inputs.  If there is no external signal, it will read
high.  However, you must program the CONTROL outputs high (taking into
account any logical inversions between the register bits and the electrical
outputs); if the open collector output is low (conducting to ground), the
external signal won't be able to pull it high (or at least not without
exceeding the specs).

The same thing can be done with totem pole outputs - program them high, and
let external logic pull them high (no problem, both pulling up) or low
(overpowering the attempt to pull high), but in this case you are overloading
the H transistor, rather than a pullup resistor, and exceeding spec, with
possible unreliability or damage.  However, this has been successfully done
with the data outputs of a conventional parallel port, and some people claim
not to have seen any damage yet.  Don't blame me if you do it and something
dies.

A third type of gate is a totem pole in which both high and low transistors
can be non-conducting at once, creating a third, floating state (this is often
called a tri-state output).  When it is in this third state, the line is not
being pulled high nor low by this device, and thus can be safely controlled
by some other device.  No pullup resistor is used.  The  74LS374 chip used
for the standard parallel port DATA outputs actually has tristate ability,
but as described elsewhere the third state is not used, and it is always
trying to pull high or low - thus my initial description of the DATA lines
as totem pole drivers.

The way true bidirectional parallel ports work is to allow the software to
selectively put the DATA outputs into the third, undriven state.  Then you
can use the data feedback register to read whatever highs or lows are put
onto the data lines externally.

Non-TTL logic, like CMOS, has the equivalents of these, but with a different
type of transistor, and different voltage and current values.  If your
parallel port uses a single chip or otherwise differs from the original
IBM parallel port, the above electrical description cannot be guaranteed,
but it is probably pretty analogous.  Let me know if you have specific
knowledge about the electical specs of your single chip parallel port, for
future versions of this document.

Note again that high and low in this description are electrical levels, as
would me measured by a voltmeter on the pins; high is associated with TTL
logic 1, but whether a given CONTROL output line is high when the
corresponding register bit is 1 or 0 varies with the line, as is described
elsewhere in this document.  The DATA lines are straight through, with no
inversions, so a 1 bit produces a high output.

23. Contributors and Information Needed for future revisions

My thanks for information, proofreading and suggestions from:
   [e-mail] (Steven M. Scharf)
   [e-mail] (Dick Dixon)
   [e-mail] (Richard Steven Walz)
   [e-mail] (George Pontis)
   [e-mail] (John Paul Morrison)

For the future:

I would like specs on the various enhanced printer ports and chipsets.

I would appreciate information on how parallel port connected Ethernet
interfaces, SCSI interfaces, tape backup units, sound cards, modems, and copy
protection devices work (which pins used how), including how "transparency"
is achieved (or not) on those with "passthrough".

I would appreciate info on data transfer programs, cables, and protocols.

I would like to hear about interrupt driven PC printer drivers, for DOS or
Unix or whatever (or why they don't work).

I would like to hear of "printer capture" software and hardware that uses
printer ports.

I would like to know about differences between "old standard" TTL parallel
ports and the LSI implementations (specific chip specs included).

I would like to hear of your interfacing projects, sucessful or not.

And of course, I'd like to hear about bugs and inaccuracies in this
document.  (Gently)

24. Differences
Version 0.92 corrected two minor typos which were kindly brought to my
attention (D2 in place of C2 in one place, and 7505 in place of 7405),
and reformatted some long lines.

Version 0.94 added a tutorial on TTL outputs.
Version 0.95 corrected the section on data xfer cables for Laplink style
programs.  Version 0.96 fixed yet more errors.

= end of Version 0.96   9/1/94   Zhahai Stewart   [e-mail]