interfacing the serial - rs-232 port part1-2.htm

Parallel Port description of the communication port

          <TR>
            <TD>
              <CENTER>Bit 3</CENTER></TD>
            <TD>Enable Modem Status Interrupt</TD></TR>
          <TR>
            <TD>
              <CENTER>Bit 2</CENTER></TD>
            <TD>Enable Receiver Line Status Interrupt</TD></TR>
          <TR>
            <TD>
              <CENTER>Bit 1</CENTER></TD>
            <TD>Enable Transmitter Holding Register Empty Interrupt</TD></TR>
          <TR>
            <TD>
              <CENTER>Bit 0</CENTER></TD>
            <TD>Enable Received Data Available 
        Interrupt</TD></TR></TBODY></TABLE><FONT size=-1>
        <CENTER>Table 7 : Interrupt Enable Register</CENTER></FONT></CENTER>
        <P></P>
        <P>The Interrupt Enable Register could possibly be one of the easiest 
        registers on a UART to understand. Setting Bit 0 high enables the 
        Received Data Available Interrupt which generates an interrupt when the 
        receiving register/FIFO contains data to be read by the CPU. </P>
        <P>Bit 1 enables Transmit Holding Register Empty Interrupt. This 
        interrupts the CPU when the transmitter buffer is empty. Bit 2 enables 
        the receiver line status interrupt. The UART will interrupt when the 
        receiver line status changes. Likewise for bit 3 which enables the modem 
        status interrupt. Bits 4 to 7 are the easy ones. They are simply 
        reserved. (If only everything was that easy!) </P>
        <P><A name=16><FONT size=+1>Interrupt Identification Register 
        (IIR)</FONT><BR>
        <HR>
        </A>
        <P></P>
        <P>
        <CENTER>
        <TABLE border=1 width="80%">
          <TBODY>
          <TR>
            <TD>
              <CENTER><B>Bit</B></CENTER></TD>
            <TD colSpan=3>
              <CENTER><B>Notes</B></CENTER></TD></TR>
          <TR>
            <TD rowSpan=4 vAlign=top>
              <CENTER>Bits 6 and 7</CENTER></TD>
            <TD>
              <CENTER>Bit 6</CENTER></TD>
            <TD>
              <CENTER>Bit 7</CENTER></TD>
            <TD>&nbsp;</TD></TR>
          <TR>
            <TD>
              <CENTER>0</CENTER></TD>
            <TD>
              <CENTER>0</CENTER></TD>
            <TD>No FIFO </TD></TR>
          <TR>
            <TD>
              <CENTER>0</CENTER></TD>
            <TD>
              <CENTER>1</CENTER></TD>
            <TD>FIFO Enabled but Unusable </TD></TR>
          <TR>
            <TD>
              <CENTER>1</CENTER></TD>
            <TD>
              <CENTER>1</CENTER></TD>
            <TD>FIFO Enabled </TD></TR>
          <TR>
            <TD>
              <CENTER>Bit 5</CENTER></TD>
            <TD colSpan=3>64 Byte Fifo Enabled (16750 only)</TD></TR>
          <TR>
            <TD>
              <CENTER>Bit 4</CENTER></TD>
            <TD colSpan=3>Reserved</TD></TR>
          <TR>
            <TD rowSpan=2 vAlign=top>
              <CENTER>Bit 3</CENTER></TD>
            <TD>
              <CENTER>0</CENTER>
            <TD colSpan=2>Reserved on 8250, 16450</TD></TR>
          <TR>
            <TD>
              <CENTER>1</CENTER>
            <TD colSpan=2>16550 Time-out Interrupt Pending</TD></TR>
          <TR>
            <TD rowSpan=5 vAlign=top>
              <CENTER>Bits 1 and 2</CENTER></TD>
            <TD>
              <CENTER>Bit 2</CENTER></TD>
            <TD>
              <CENTER>Bit 1</CENTER></TD>
            <TD>&nbsp; </TD></TR>
          <TR>
            <TD>
              <CENTER>0</CENTER></TD>
            <TD>
              <CENTER>0</CENTER></TD>
            <TD>Modem Status Interrupt </TD></TR>
          <TR>
            <TD>
              <CENTER>0</CENTER></TD>
            <TD>
              <CENTER>1</CENTER></TD>
            <TD>Transmitter Holding Register Empty Interrupt</TD></TR>
          <TR>
            <TD>
              <CENTER>1</CENTER></TD>
            <TD>
              <CENTER>0</CENTER></TD>
            <TD>Received Data Available Interrupt</TD></TR>
          <TR>
            <TD>
              <CENTER>1</CENTER></TD>
            <TD>
              <CENTER>1</CENTER></TD>
            <TD>Receiver Line Status Interrupt</TD></TR>
          <TR>
            <TD rowSpan=2 vAlign=top>
              <CENTER>Bit 0</CENTER></TD>
            <TD>
              <CENTER>0</CENTER>
            <TD colSpan=2>Interrupt Pending</TD></TR>
          <TR>
            <TD>
              <CENTER>1</CENTER>
            <TD colSpan=2>No Interrupt Pending</TD></TR></TBODY></TABLE><FONT 
        size=-1>
        <CENTER>Table 8 : Interrupt Identification Register 
        </CENTER></FONT></CENTER>
        <P>The interrupt identification register is a read only register. Bits 6 
        and 7 give status on the FIFO Buffer. When both bits are '0' no FIFO 
        buffers are active. This should be the only result you will get from a 
        8250 or 16450. If bit 7 is active but bit 6 is not active then the UART 
        has it's buffers enabled but are unusable. This occurs on the 16550 UART 
        where a bug in the FIFO buffer made the FIFO's unusable. If both bits 
        are '1' then the FIFO buffers are enabled and fully operational. </P>
        <P>Bits 4 and 5 are reserved. Bit 3 shows the status of the time-out 
        interrupt on a 16550 or higher. </P>
        <P>Lets jump to Bit 0 which shows whether an interrupt has occurred. If 
        an interrupt has occurred it's status will shown by bits 1 and 2. These 
        interrupts work on a priority status. The Line Status Interrupt has the 
        highest Priority, followed by the Data Available Interrupt, then the 
        Transmit Register Empty Interrupt and then the Modem Status Interrupt 
        which has the lowest priority. </P>
        <P></P>
        <P><A name=17></A><FONT size=+1>First In / First Out Control Register 
        (FCR)</FONT><BR>
        <HR>

        <P></P>
        <P>
        <CENTER>
        <TABLE border=1 width="80%">
          <TBODY>
          <TR>
            <TD>
              <CENTER><B>Bit</B></CENTER></TD>
            <TD colSpan=3>
              <CENTER><B>Notes</B></CENTER></TD></TR>
          <TR>
            <TD rowSpan=5 vAlign=top>
              <CENTER>Bits 6 and 7</CENTER></TD>
            <TD>
              <CENTER>Bit 7</CENTER></TD>
            <TD>
              <CENTER>Bit 6</CENTER></TD>
            <TD>Interrupt Trigger Level </TD></TR>
          <TR>
            <TD>
              <CENTER>0</CENTER></TD>
            <TD>
              <CENTER>0</CENTER></TD>
            <TD>1 Byte </TD></TR>
          <TR>
            <TD>
              <CENTER>0</CENTER></TD>
            <TD>
              <CENTER>1</CENTER></TD>
            <TD>4 Bytes </TD></TR>
          <TR>
            <TD>
              <CENTER>1</CENTER></TD>
            <TD>
              <CENTER>0</CENTER></TD>
            <TD>8 Bytes </TD></TR>
          <TR>
            <TD>
              <CENTER>1</CENTER></TD>
            <TD>
              <CENTER>1</CENTER></TD>
            <TD>14 Bytes</TD></TR>
          <TR>
            <TD>
              <CENTER>Bit 5</CENTER></TD>
            <TD colSpan=3>Enable 64 Byte FIFO (16750 only)</TD></TR>
          <TR>
            <TD>
              <CENTER>Bit 4</CENTER></TD>
            <TD colSpan=3>Reserved</TD></TR>
          <TR>
            <TD>
              <CENTER>Bit 3</CENTER></TD>
            <TD colSpan=3>DMA Mode Select. Change status of RXRDY &amp; TXRDY 
              pins from mode 1 to mode 2.</TD></TR>
          <TR>
            <TD>
              <CENTER>Bit 2</CENTER></TD>
            <TD colSpan=3>Clear Transmit FIFO</TD></TR>
          <TR>
            <TD>
              <CENTER>Bit 1</CENTER></TD>
            <TD colSpan=3>Clear Receive FIFO</TD></TR>
          <TR>
            <TD>
              <CENTER>Bit 0</CENTER></TD>
            <TD colSpan=3>Enable FIFO's</TD></TR></TBODY></TABLE><FONT size=-1>
        <CENTER>Table 9 : FIFO Control Register </CENTER></FONT></CENTER>
        <P></P>
        <P>The FIFO register is a write only register. This register is used to 
        control the FIFO (First In / First Out) buffers which are found on 
        16550's and higher. </P>
        <P>Bit 0 enables the operation of the receive and transmit FIFO's. 
        Writing a '0' to this bit will disable the operation of transmit and 
        receive FIFO's, thus you will loose all data stored in these FIFO 
        buffers. </P>
        <P>Bit's 1 and 2 control the clearing of the transmit or receive FIFO's. 
        Bit 1 is responsible for the receive buffer while bit 2 is responsible 
        for the transmit buffer. Setting these bits to 1 will only clear the 
        contents of the FIFO and will not affect the shift registers. These two 
        bits are self resetting, thus you don't need to set the bits to '0' when 
        finished. </P>Bit 3 enables the DMA mode select which is found on 16550 
        UARTs and higher. More on this later. Bits 4 and 5 are those easy type 
        again, Reserved. 
        <P></P>
        <P>Bits 6 and 7 are used to set the triggering level on the Receive 
        FIFO. For example if bit 7 was set to '1' and bit 6 was set to '0' then 
        the trigger level is set to 8 bytes. When there is 8 bytes of data in 
        the receive FIFO then the Received Data Available interrupt is set. See 
        (IIR) </P>
        <P><A name=18></A><FONT size=+1>Line Control Register (LCR)</FONT><BR>
        <HR>

        <P></P>
        <P>
        <CENTER>
        <TABLE border=1 width="80%">
          <TBODY>
          <TR>
            <TD rowSpan=2 vAlign=top>
              <CENTER>Bit 7</CENTER></TD>
            <TD>
              <CENTER>1</CENTER>
            <TD colSpan=3>Divisor Latch Access Bit</TD></TR>
          <TR>
            <TD>
              <CENTER>0</CENTER>
            <TD colSpan=3>Access to Receiver buffer, Transmitter buffer &amp; 
              Interrupt Enable Register</TD></TR>
          <TR>
            <TD>
              <CENTER>Bit 6</CENTER></TD>
            <TD colSpan=4>Set Break Enable</TD></TR>
          <TR>
            <TD rowSpan=6 vAlign=top>
              <CENTER>Bits 3, 4 And 5</CENTER></TD>
            <TD width="8%">
              <CENTER>Bit 5</CENTER></TD>
            <TD width="8%">
              <CENTER>Bit 4</CENTER></TD>
            <TD width="8%">
              <CENTER>Bit 3</CENTER></TD>
            <TD>Parity Select</TD></TR>
          <TR>
            <TD>
              <CENTER>X</CENTER></TD>
            <TD>
              <CENTER>X</CENTER></TD>
            <TD>
              <CENTER>0</CENTER></TD>
            <TD>No Parity </TD></TR>
          <TR>
            <TD>
              <CENTER>0</CENTER></TD>
            <TD>
              <CENTER>0</CENTER></TD>
            <TD>
              <CENTER>1</CENTER></TD>
            <TD>Odd Parity </TD></TR>
          <TR>
            <TD>
              <CENTER>0</CENTER></TD>
            <TD>
              <CENTER>1</CENTER></TD>
            <TD>
              <CENTER>1</CENTER></TD>
            <TD>Even Parity </TD></TR>
          <TR>
            <TD>
              <CENTER>1</CENTER></TD>
            <TD>
              <CENTER>0</CENTER></TD>
            <TD>
              <CENTER>1</CENTER></TD>
            <TD>High Parity (Sticky)</TD></TR>
          <TR>
            <TD>
              <CENTER>1</CENTER></TD>
            <TD>
              <CENTER>1</CENTER></TD>
            <TD>
              <CENTER>1</CENTER></TD>
            <TD>Low Parity (Sticky)</