xp_atom_reg.h

IBM source for pallas/vulcan/vesta

/*----------------------------------------------------------------------------+
|       This source code has been made available to you by IBM on an AS-IS
|       basis.  Anyone receiving this source is licensed under IBM
|       copyrights to use it in any way he or she deems fit, including
|       copying it, modifying it, compiling it, and redistributing it either
|       with or without modifications.  No license under IBM patents or
|       patent applications is to be implied by the copyright license.
|
|       Any user of this software should understand that IBM cannot provide
|       technical support for this software and will not be responsible for
|       any consequences resulting from the use of this software.
|
|       Any person who transfers this source code or any derivative work
|       must include the IBM copyright notice, this paragraph, and the
|       preceding two paragraphs in the transferred software.
|
|       COPYRIGHT   I B M   CORPORATION 1998
|       LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
+----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------+
| Author:    Paul Gramann
| Component: xp
| File:      xp_atom_reg.h
| Purpose:   Transport defines.
|
| Changes:
| Date:      Author  Comment:
| ---------  ------  --------
| 05-Apr-99  PAG     Created
| 04-May-99  PAG     Placed in library
| 1m-May-99  MPT     Changed "pack" pragma
| 20-Jan-00  TJC     Updated for Vesta.
| 30-Apr-01  TJC     Updated for Pallas.
| 01-Sep-01  LGH     Combine the three devices dcr definition, ported to Linux
+----------------------------------------------------------------------------*/

#ifndef XP_REG_H
#define XP_REG_H

#include <hw/hardware.h>

#pragma pack(1)
/*----------------------------------------------------------------------------+
|  Register Defines
+----------------------------------------------------------------------------*/
#ifndef __DRV_FOR_VESTA__       // for vulcan and pallas ...
#define XP_CONFIG3_INSEL_CI0     0     /* input select to CIO Interface      */

#ifdef __DRV_FOR_PALLAS__
#define XP_CONFIG3_INSEL_CI1     1     /* input select to CI1 Interface      */
#define XP_CONFIG3_INSEL_1394    2     /* input select to 1394 Interface     */
#endif
#endif
//Only make sense to device XP0
#define XP_CONFIG3_INSEL_PVR     3     /* input select to PVR mode           */

/*----------------------------------------------------------------------------+
|  CONFIGURATION 1 REGISTER
|  Location Address: 0x0000
+----------------------------------------------------------------------------*/
typedef struct xp_config1_type {
    //The following 4 fields make bo sense to XP0
    unsigned tsrc        : 1;          /* Auxiliary Port 1394 Compatiability */
    unsigned axclkp      : 1;          /* 1=Rising edge of AX_CLOCK,0=falling*/
    unsigned axced       : 3;          /* Auxilliary Clock Edge Delay        */
    unsigned aec         : 3;          /* Auxilliary Extend Clock            */

    unsigned denbl       : 1;          /* 1=descrambler enabled, 0=disabled  */
//the following 5 fields only make sense to XP0
    unsigned res2        : 2;
    unsigned vpu         : 1;          /* 1=force vid packets also to Q31/BQ */
    unsigned apu         : 1;          /* 1=force aud packets also to Q30/BQ */
    unsigned apwma       : 1;          /* 1=adjust     PWM, 0=no adjusted    */
    unsigned tstoe       : 1;          /* 1=TS timeout enable, 0=disabled    */
//the following 5 fields make no senses to XP0
    unsigned axdp        : 1;          /* 1=AX_DATA inverted, 0=unmodified   */
    unsigned res3        : 1;
    unsigned axsp        : 1;          /* 1=start polarity low act,0=high    */
    unsigned axep        : 1;          /* 1=error polarity low act,0=high    */
    unsigned axdvp       : 1;          /* 1=data val polarity low act,0=high */

    unsigned tsclkp      : 1;          /* 1=data latched on clock FE, 0=RE   */
    unsigned tsdp        : 1;          /* 1=CI_DATA inverted, 0=not inverted */

#ifdef __DRV_FOR_PALLAS__
    unsigned tssp        : 1;          /* 1=CI_PACKET_START low act, 0=high  */
    unsigned tsep        : 1;          /* 1=CI_DATA_ERROR low active,0=high  */
#else
    unsigned res4        : 2;
#endif

    unsigned tsvp        : 1;          /* 1=CI_DATA_ENABLE low input,0=high  */

#ifdef __DRV_FOR_PALLAS__
    unsigned tssm        : 1;          /* 1=CI_PACKET_START used, 0=not used */
#else
    unsigned res5        : 1;
#endif

    unsigned syncd       : 2;          /* no. of syncbytes +1 dropped        */
    unsigned bbmode      : 1;          /* 1=bit mode, 0=byte mode            */
    unsigned syncl       : 3;          /* no. of sync bytes+1 before in sync */

} XP_CONFIG1_REG, *XP_CONFIG1_REGP;

/*----------------------------------------------------------------------------+
|  CONTROL1 REGISTER
|  Location Address: 0x0001
+----------------------------------------------------------------------------*/
typedef struct xp_control1_type {
    unsigned res1        :25;
    unsigned sbe         : 1;          /* 1=bypass, 0=scan for 0x47 in stream*/
    unsigned pbe         : 1;          /* 1=parser bypass enabled, 0=disabled*/
    unsigned res2        : 1;
    unsigned senbl       : 1;          /* 1=bit mode, 0=byte mode            */
    unsigned sdop        : 1;          /* 1=disable packet sync, 0=no action */
    unsigned res3        : 1;
    unsigned swrst       : 1;          /* 1=reset transport                  */
} XP_CONTROL1_REG, *XP_CONTROL1_REGP;

/*----------------------------------------------------------------------------+
|  CONFIGURATION 3 REGISTER
|  Location Address: 0x0006
+----------------------------------------------------------------------------*/
typedef struct xp_config3_type {
    unsigned res1        :21;
    unsigned insel       : 2;          /* Input Sel:0=CI0,1=CI1,2=1394,3=PVR */
//make no sense to XP0
    unsigned api         : 5;          /* Auxiliary Packet Interval          */
    unsigned dmode       : 1;          /* Descrambler Mode                   */
    unsigned res3        : 3;
} XP_CONFIG3_REG, *XP_CONFIG3_REGP;

/*----------------------------------------------------------------------------+
|  PWM REGISTER
|  Location Address: 0x0016
+----------------------------------------------------------------------------*/
typedef struct xp_pwm_type {
    unsigned res1        :20;
    unsigned pwm         :12;          /* Pulse width modulator              */
} XP_PWM_REG;

/*----------------------------------------------------------------------------+
|  PCR-STC THRESHOLD REGISTER
|  Location Address: 0x0017
+----------------------------------------------------------------------------*/
typedef struct xp_pcrstct_type {
    unsigned res1        :14;
    unsigned pcrt        :18;          /* PCR Threshold                      */
} XP_PCRSTCT_REG;

/*----------------------------------------------------------------------------+
|  PCR-STC DELTA REGISTER
|  Location Address: 0x0018
+----------------------------------------------------------------------------*/
typedef struct xp_pcrstcd_type {
    unsigned res1        :12;
    unsigned ovfl        : 1;          /* overflow                           */
    unsigned sign        : 1;          /* sign, 0=PCR < STC, 1=PCR > STC     */
    unsigned delta       :18;          /* delta between latched PCR and STC  */