av_dcr.h

IBM source for pallas/vulcan/vesta

/*----------------------------------------------------------------------------+
|       This source code has been made available to you by IBM on an AS-IS
|       basis.  Anyone receiving this source is licensed under IBM
|       copyrights to use it in any way he or she deems fit, including
|       copying it, modifying it, compiling it, and redistributing it either
|       with or without modifications.  No license under IBM patents or
|       patent applications is to be implied by the copyright license.
|
|       Any user of this software should understand that IBM cannot provide
|       technical support for this software and will not be responsible for
|       any consequences resulting from the use of this software.
|
|       Any person who transfers this source code or any derivative work
|       must include the IBM copyright notice, this paragraph, and the
|       preceding two paragraphs in the transferred software.
|
|       COPYRIGHT   I B M   CORPORATION 1998
|       LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
+----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------+
|   Author    :  Lin Guo Hui
|   Component :  xp
|   File      :  av_dcr.c
|   Purpose   :  DCR access to A/V Registers for Chan Chan using
|   Changes   :
|
|   Date       By   Comments
|   ---------  ---  --------------------------------------------------------
|       30-Sep-01  LGH  Create
|
+----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------+
| Video decoder.  Suspect 0x179, 0x169, 0x16a, 0x152 (rc).
+----------------------------------------------------------------------------*/
#define v_c_cntl        0x140   /* control decoder operation */
#define v_c_mode        0x141   /* video operational mode */
#define v_s_stc0        0x142   /* STC high order bits 31:0 */
#define v_s_stc1        0x143   /* STC low order bit 32 */
#define v_s_pts0        0x144   /* wPTS high order bits 31:0 */
#define v_s_pts1        0x145   /* wPTS low order bit 32 */
#define v_fifo          0x146   /* FIFO data port */
#define v_fifo_s        0x147   /* FIFO status */
#define v_cmd           0x148   /* wsend command to decoder */
#define v_cmd_d         0x149   /* port for command params */
#define v_cmd_st        0x14A   /* command status */
#define v_cmd_ad        0x14B   /* command address */
#define v_procia        0x14C   /* instruction store */
#define v_procid        0x14D   /* data port for I_Store */
#define v_osd_m         0x151   /* OSD mode control */
#define v_host_i        0x152   /* rbase interrupt register */
#define v_mask          0x153   /* interrupt mask register */
#define v_dispm         0x154   /* operational mode for Disp */
#define v_dispd         0x155   /* setting for 'Sync' delay */
#define v_vb_ctl        0x156   /* VBI */
#define v_displb        0x157   /* set left border of display */
#define v_disptb        0x158   /* top border of display */
#define v_osd_la        0x159   /* first link address for OSD */
#define v_rb_thr        0x15B   /* rate buffer threshold */
#define v_stc_ca        0x15D   /* STC common address */
#define v_ptsctl        0x15F   /* PTS Control */
#define v_w_prot        0x165   /* write protect for I_Store */
#define v_vc_qa         0x167   /* video clip queued block Ad */
#define v_vc_ql         0x168   /* video clip queued block Le */
#define v_udbase        0x16B   /* base mem add for user data */
#define v_v0base        0x16C   /* base mem add for VBI-0 */
#define v_v1base        0x16D   /* base mem add for VBI-1 */
#define v_osbase        0x16E   /* base mem add for OSD data */
#define v_rbbase        0x16F   /* base mem add for video buf */
#define v_dramad        0x170   /* DRAM address */
#define v_dramdt        0x171   /* data port for DRAM access */
#define v_dramcs        0x172   /* DRAM command and statusa */
#define v_vc_wa         0x173   /* rv clip work address */
#define v_vc_wl         0x174   /* rv clip work length */
#define v_m_seg0        0x175   /* segment address 0 */
#define v_m_seg1        0x176   /* segment address 1 */
#define v_m_seg2        0x177   /* segment address 2 */
#define v_m_seg3        0x178   /* segment address 3 */
#define v_fbuff_base    0x179   /* frame buffer base memory */
#define v_tl_border     0x17B   /* top left border */
#define v_tr_dly        0x17C   /* transparency gate delay */
#define v_small_board   0x17D   /* left/top small pict. bord. */
#define v_hv_zoom       0x17E   /* hor/ver zoom window */
#define v_rb_sz         0x17F   /* rate buffer size read */

/*----------------------------------------------------------------------------+
| Audio decoder. Suspect 0x1ad, 0x1b4, 0x1a3, 0x1a5 (read/write status)
+----------------------------------------------------------------------------*/
#define a_ctrl0         0x1a0   /* control 0 */
#define a_ctrl1         0x1a1   /* control 1 */
#define a_ctrl2         0x1a2   /* control 2 */
#define a_command       0x1a3   /* wcommand register */
#define a_isr           0x1a4   /* rinterrupt status register */
#define a_imr           0x1a5   /* winterrupt mask register */
#define a_dsr           0x1a6   /* rdecoder status register */
#define a_stc           0x1a7   /* system time clock */
#define a_csr           0x1a8   /* channel status register */
#define a_latcnt        0x1a9   /* PLB Latency count */
#define a_pts           0x1aa   /* rpresentation time stamp */
#define a_tgctrl        0x1ab   /* tone generation control */
#define a_tgval         0x1ac   /* tone generation value */
#define a_auxd          0x1ad   /* raux data */
#define a_strmid        0x1ae   /* stream ID */
#define a_sqar          0x1af   /* queued address register */
#define a_dsp_st        0x1b0   /* rDSP status */
#define a_qlr           0x1b1   /* queued len address */
#define a_dsp_c         0x1b2   /* DSP control */
#define a_inst_d        0x1b4   /* winstruction download */
#define a_war           0x1b5   /* rworking address register */
#define a_seg1r         0x1b6   /* segment 1 base register */
#define a_seg2r         0x1b7   /* segment 2 base register */
#define a_atf           0x1b9   /* audio att value front */
#define a_atr           0x1ba   /* audio att value rear */
#define a_atc           0x1bb   /* audio att value center */
#define a_seg3r         0x1bc   /* segment 3 base register */
#define a_offset        0x1bd   /* offset address */
#define a_wrl           0x1be   /* working length register */
#define a_plb_pr        0x1bf   /* PLB priority */

/*-----------------------------------------------------------------------------+
| Bit definitions for the MPEG audio registers.
+-----------------------------------------------------------------------------*/
#define DECOD_AUD_CTRL0_MODE_MASK       0x0000C000
#define DECOD_AUD_CTRL0_MODE_L          0x00000000
#define DECOD_AUD_CTRL0_MODE_SL         0x00004000
#define DECOD_AUD_CTRL0_MODE_C          0x00008000
#define DECOD_AUD_CTRL0_START_DECODER   0x00000400
#define DECOD_AUD_CTRL0_ENABLE_SYNC     0x00000200
#define DECOD_AUD_CTRL0_START_PARSING   0x00000100
#define DECOD_AUD_CTRL0_CLIP_EN         0x00000080
#define DECOD_AUD_CTRL0_DOWNLOAD_END    0x00000040
#define DECOD_AUD_CTRL0_DOWNLOAD_EN     0x00000008
#define DECOD_AUD_CTRL0_ENABLE_INT      0x00000004
#define DECOD_AUD_CTRL0_TYPE_MASK       0x00000003
#define DECOD_AUD_CTRL0_TYPE_ES         0x00000001
#define DECOD_AUD_CTRL0_TYPE_PES        0x00000002
#define DECOD_AUD_CTRL0_TYPE_MPEG1      0x00000003

#define DECOD_AUD_CTRL1_SOFT_MUTE       0x00000400

#define DECOD_AUD_CTRL2_KM1             0x00008000
#define DECOD_AUD_CTRL2_MUTE            0x00004000
#define DECOD_AUD_CTRL2_KM2             0x00002000
#define DECOD_AUD_CTRL2_IP              0x00001000
#define DECOD_AUD_CTRL2_ID              0x00000800
#define DECOD_AUD_CTRL2_HD              0x00000400
#define DECOD_AUD_CTRL2_DM              0x00000200
#define DECOD_AUD_CTRL2_RF              0x00000100
#define DECOD_AUD_CTRL2_LL              0x00000080
#define DECOD_AUD_CTRL2_HL              0x00000040
#define DECOD_AUD_CTRL2_DN              0x00000020
#define DECOD_AUD_CTRL2_DE              0x00000010
#define DECOD_AUD_CTRL2_OM              0x00000008
#define DECOD_AUD_CTRL2_KM0             0x00000004
#define DECOD_AUD_CTRL2_AC3             0x00000000
#define DECOD_AUD_CTRL2_MPEG            0x00000001
#define DECOD_AUD_CTRL2_PCM             0x00000003

#define DECOD_AUD_CMD_RESET             0x00000000

#define DECOD_AUD_INT_CCC               0x00008000
#define DECOD_AUD_INT_RTBC              0x00004000
#define DECOD_AUD_INT_ED                0x00000800
#define DECOD_AUD_INT_PE                0x00000400
#define DECOD_AUD_INT_BE                0x00000200
#define DECOD_AUD_INT_BF                0x00000100
#define DECOD_AUD_INT_PSE               0x00000080
#define DECOD_AUD_INT_PTO               0x00000040
#define DECOD_AUD_INT_ADO               0x00000020
#define DECOD_AUD_INT_ADD               0x00000010
#define DECOD_AUD_INT_CM                0x00000001
#define DECOD_AUD_INT_ALL               0x0000CFF1

#define DECOD_AUD_DSR_CHAN_CH           0x00008000
#define DECOD_AUD_DSR_TB_CH_IN_PROC     0x00004000
#define DECOD_AUD_DSR_ERROR_MASK        0x00000C00
#define DECOD_AUD_DSR_AUX_DATA          0x00000010
#define DECOD_AUD_DSR_COMMAND_COM       0x00000002

#define DECOD_AUD_TONE_CTRL_TR          0x00000008
#define DECOD_AUD_TONE_CTRL_BA_MASK     0x00000007

#define DECOD_AUD_TONE_VALUE_BD_MASK    0x00001F00
#define DECOD_AUD_TONE_VALUE_FI_MASK    0x00001F7F

#define DECOD_AUD_QLR_BV                0x80000000
#define DECOD_AUD_QLR_SB                0x20000000
#define DECOD_AUD_QLR_QL_MASK           0x001FFFFF

#define DECOD_AUD_SEG_ALIGN             0x0000007F
#define DECOD_AUD_SEG_SH                7

/*-----------------------------------------------------------------------------+
| MPEG audio defines.
+-----------------------------------------------------------------------------*/
#define DECOD_AUD_AC3                   0x00000001
#define DECOD_AUD_LPCM                  0x00000002
#define DECOD_AUD_MPEG                  0x00000003
#define DECOD_AUD_PCM                   0x00000004

#define DECOD_AUD_STREAM_MPEG           0
#define DECOD_AUD_STREAM_PES            1
#define DECOD_AUD_STREAM_ES             2