xp_atom_dcr.c

IBM source for pallas/vulcan/vesta

    case 1:

        MT_DCR(XPT1_LR,ulAddress);

        ulData = MF_DCR(XPT1_DT);

        break;

    case 2:

        MT_DCR(XPT2_LR,ulAddress);

        ulData = MF_DCR(XPT2_DT);

        break;
#endif

    default:

        break;

    }



    return(ulData);

}



/*----------------------------------------------------------------------------+

|   xp_atom_dcr_read_register_channel

+----------------------------------------------------------------------------*/

short xp_atom_dcr_read_register_channel(UINT uDeviceIndex,XP_DCR_REGISTER_TYPE regtype,

                                        SHORT wId,ULONG *pData)

{

    ULONG                  ulAddr;

    ULONG                  ulValue;

    XP_PID_FILTER_REGP     pPid;

    XP_QCONFIGB_REGP       pCb;

    XP_FILTER_CONTROL_REGP pFilter;

    XP_QSTATB_REGP         pQb;

    XP_QSTATD_REGP         pQd;



    /*------------------------------------------------------------------------+

    |  Read the value from hardware

    +------------------------------------------------------------------------*/

    switch(regtype) {

        case XP_PID_FILTER_REG_PIDV:

            ulAddr    = XP_DCR_ADDR_BASE_PID + wId;

            ulValue   = xp_atom_dcr_read(uDeviceIndex,ulAddr);

            pPid    = (XP_PID_FILTER_REGP)(void *) &ulValue;

            *pData = pPid->pidv;

            break;



        case XP_QCONFIGB_REG_DTYPE:

            ulAddr    = XP_DCR_ADDR_BASE_QCONFIGAB + (wId * 2) + 1;

            ulValue   = xp_atom_dcr_read(uDeviceIndex,ulAddr);

            pCb     = (XP_QCONFIGB_REGP)(void *) &ulValue;

            *pData = pCb->dtype;

            break;



        case XP_QCONFIGB_REG_ENBL:

            ulAddr    = XP_DCR_ADDR_BASE_QCONFIGAB + (wId * 2) + 1;

            ulValue   = xp_atom_dcr_read(uDeviceIndex,ulAddr);

            pCb     = (XP_QCONFIGB_REGP)(void *) &ulValue;

            *pData = pCb->enbl;

            break;



        case XP_QCONFIGB_REG_RPTR:

            ulAddr    = XP_DCR_ADDR_BASE_QCONFIGAB + (wId * 2) + 1;

            ulValue   = xp_atom_dcr_read(uDeviceIndex,ulAddr);

            pCb     = (XP_QCONFIGB_REGP)(void *) &ulValue;



            /*----------------------------------------------------------------+

            |  Convert from a 256 byte block

            +----------------------------------------------------------------*/

            *pData = pCb->rptr << 8;

            break;



        case XP_FILTER_CONTROL_REG_ENBL:

            ulAddr    = XP_DCR_ADDR_BASE_FILTER + (wId * 4);

            ulValue   = xp_atom_dcr_read(uDeviceIndex,ulAddr);

            pFilter = (XP_FILTER_CONTROL_REGP)(void *) &ulValue;

            *pData = pFilter->enbl;

            break;



        case XP_FILTER_CONTROL_REG_NFILT:

            ulAddr    = XP_DCR_ADDR_BASE_FILTER + (wId * 4);

            ulValue   = xp_atom_dcr_read(uDeviceIndex,ulAddr);

            pFilter = (XP_FILTER_CONTROL_REGP)(void *) &ulValue;

            *pData = pFilter->nfilt;

            break;



        case XP_QCONFIGB_REG_FSF:

            ulAddr    = XP_DCR_ADDR_BASE_QCONFIGAB + (wId * 2) + 1;

            ulValue   = xp_atom_dcr_read(uDeviceIndex,ulAddr);

            pCb     = (XP_QCONFIGB_REGP)(void *) &ulValue;

            *pData = pCb->fsf;

            break;



        case XP_QSTATB_REG_WPTR:

            ulAddr    = XP_DCR_ADDR_BASE_QSTATABCD + (wId * 4) + 1;

            ulValue   = xp_atom_dcr_read(uDeviceIndex,ulAddr);

            pQb     = (XP_QSTATB_REG *)(void *) &ulValue;

            *pData = pQb->wptr;

            break;



        case XP_QSTATD_REG_WSTART:

            ulAddr    = XP_DCR_ADDR_BASE_QSTATABCD + (wId * 4) + 3;

            ulValue   = xp_atom_dcr_read(uDeviceIndex,ulAddr);

            pQd     = (XP_QSTATD_REG *)(void *) &ulValue;

            *pData = pQd->wstart;

            break;



        default:

            return(-1);

    }



    return(0);

}



/*----------------------------------------------------------------------------+

|   xp_atom_dcr_write

+-----------------------------------------------------------------------------+

|

|   DESCRIPTION:  write to a demux DCR register

|

|   PROTOTYPE  :  void xp_atom_dcr_write(

|                 unsigned long address,

|                 unsigned long data)

|

|   ARGUMENTS  :  address      -  demux DCR address to write

|                 data         -  data to write to the 'address'

|

|   RETURNS    :

|

|   ERRORS     :

|

|   COMMENTS   :  The transport demux uses indirect DCR addressing.  An DCR

|                 register (0x180) is first written with the demux index,

|                 and then a write operation is performed using the 'data'

|                 argument.  A critical section must surround this indirect

|                 addressing to eliminate any interrupts which could affect

|                 the operation.

|

+----------------------------------------------------------------------------*/

void xp_atom_dcr_write(UINT uDeviceIndex,ULONG ulAddress,ULONG ulData)

{



    switch (uDeviceIndex)

    {

    case 0:

        MT_DCR(XPT0_LR,ulAddress);

        MT_DCR(XPT0_DT,ulData);

        break;

#ifdef __DRV_FOR_PALLAS__

    case 1:

        MT_DCR(XPT1_LR,ulAddress);

        MT_DCR(XPT1_DT,ulData);

        break;

    case 2:

        MT_DCR(XPT2_LR,ulAddress);

        MT_DCR(XPT2_DT,ulData);

        break;
#endif

    default:

        break;

    }



 }



/*----------------------------------------------------------------------------+

|   xp_atom_dcr_write_register_channel

+----------------------------------------------------------------------------*/

SHORT xp_atom_dcr_write_register_channel(UINT uDeviceIndex,XP_DCR_REGISTER_TYPE regtype,

                                         SHORT wId,ULONG ulData)

{

    ULONG ulAddr;

    ULONG ulValue;

    XP_PID_FILTER_REGP     pPid;

    XP_QCONFIGA_REGP       pCa;

    XP_QCONFIGB_REGP       pCb;

    XP_QSTATB_REGP         pQb;

    XP_QSTATD_REGP         pQd;

    XP_FILTER_CONTROL_REGP pFilter;



    /*------------------------------------------------------------------------+

    |  Read the ulValue from hardware

    +------------------------------------------------------------------------*/

    switch(regtype) {

        case XP_PID_FILTER_REG_PIDV:

            ulAddr        = XP_DCR_ADDR_BASE_PID + wId;

            ulValue       = xp_atom_dcr_read(uDeviceIndex,ulAddr);

            pPid        = (XP_PID_FILTER_REGP)(void *) &ulValue;

            pPid->pidv  = ulData;

            break;



        case XP_QCONFIGB_REG_DTYPE:

            ulAddr        = XP_DCR_ADDR_BASE_QCONFIGAB + (wId * 2) + 1;

            ulValue       = xp_atom_dcr_read(uDeviceIndex,ulAddr);

            pCb         = (XP_QCONFIGB_REGP)(void *) &ulValue;

            pCb->dtype  = ulData;



            /*----------------------------------------------------------------+

            |  If the unload type is for streaming data, then use

            |  the BTI interrupt and set the Boundary Threshold (queueInt)

            |  to interrupt every 512 bytes.

            +----------------------------------------------------------------*/

            if(ulData < 8) {

                pCb->scpc = 0;

                xp_atom_dcr_write_register_channel(uDeviceIndex,XP_QCONFIGA_REG_BTHRES, wId, 2);

            }

            else {

                pCb->scpc = 1;

                xp_atom_dcr_write_register_channel(uDeviceIndex,XP_QCONFIGA_REG_BTHRES, wId, 0);

            }

            break;



        case XP_QCONFIGB_REG_ENBL:

            ulAddr        = XP_DCR_ADDR_BASE_QCONFIGAB + (wId * 2) + 1;

            ulValue       = xp_atom_dcr_read(uDeviceIndex,ulAddr);

            pCb         = (XP_QCONFIGB_REGP)(void *) &ulValue;

            pCb->enbl   = ulData;

            break;



        case XP_QCONFIGA_REG_BTHRES:

            ulAddr        = XP_DCR_ADDR_BASE_QCONFIGAB + (wId * 2);

            ulValue       = xp_atom_dcr_read(uDeviceIndex,ulAddr);

            pCa         = (XP_QCONFIGA_REGP)(void *) &ulValue;

            pCa->bthres = ulData;

            break;



        case XP_QCONFIGB_REG_RPTR:

            ulAddr        = XP_DCR_ADDR_BASE_QCONFIGAB + (wId * 2) + 1;

            ulValue       = xp_atom_dcr_read(uDeviceIndex,ulAddr);

            pCb         = (XP_QCONFIGB_REGP)(void *) &ulValue;

            /*----------------------------------------------------------------+

            |  Convert to a 256 byte block

            +----------------------------------------------------------------*/

            pCb->rptr   = ulData >> 8;

            break;



        case XP_FILTER_CONTROL_REG_ENBL:

            ulAddr           = XP_DCR_ADDR_BASE_FILTER + (wId * 4);

            ulValue          = xp_atom_dcr_read(uDeviceIndex,ulAddr);

            pFilter        = (XP_FILTER_CONTROL_REGP)(void *) &ulValue;

            pFilter->enbl  = ulData;

            break;



        case XP_FILTER_CONTROL_REG_NFILT:

            ulAddr           = XP_DCR_ADDR_BASE_FILTER + (wId * 4);

            ulValue          = xp_atom_dcr_read(uDeviceIndex,ulAddr);

            pFilter        = (XP_FILTER_CONTROL_REGP)(void *) &ulValue;

            pFilter->nfilt = ulData;

            break;



        case XP_FILTER_CONTROL_REG_SFID:

            ulAddr           = XP_DCR_ADDR_BASE_FILTER + (wId * 4);

            ulValue          = xp_atom_dcr_read(uDeviceIndex,ulAddr);

            pFilter        = (XP_FILTER_CONTROL_REGP)(void *) &ulValue;

            pFilter->sfid  = ulData;

            break;



        case XP_QCONFIGB_REG_FSF:

            ulAddr           = XP_DCR_ADDR_BASE_QCONFIGAB + (wId * 2) + 1;

            ulValue          = xp_atom_dcr_read(uDeviceIndex,ulAddr);

            pCb            = (XP_QCONFIGB_REGP)(void *) &ulValue;

            pCb->fsf       = ulData;

            break;



        case XP_QSTATB_REG_WPTR:

            ulAddr           = XP_DCR_ADDR_BASE_QSTATABCD + (wId * 4) + 1;

            ulValue          = xp_atom_dcr_read(uDeviceIndex,ulAddr);

            pQb            = (XP_QSTATB_REG *)(void *) &ulValue;

            pQb->wptr      = ulData;

            break;



        case XP_QSTATD_REG_WSTART:

            ulAddr           = XP_DCR_ADDR_BASE_QSTATABCD + (wId * 4) + 3;

            ulValue          = xp_atom_dcr_read(uDeviceIndex,ulAddr);

            pQd            = (XP_QSTATD_REG *)(void *) &ulValue;

            pQd->wstart    = ulData;

            break;



        default:

            return(-1);

    }



    xp_atom_dcr_write(uDeviceIndex,ulAddr, ulValue);



    return(0);

}

void xp_atom_disable_aud_sync()
{
    ULONG reg;

    reg = MF_DCR(a_ctrl0) & (~DECOD_AUD_CTRL0_ENABLE_SYNC);
    MT_DCR(a_ctrl0,reg);
}

void xp_atom_disable_vid_sync()
{
    ULONG reg;

    reg = MF_DCR(v_c_cntl) |DECOD_CHIP_CONTROL_DIS_SYNC;
    MT_DCR(v_c_cntl,reg);
}

int xp_atom_a_hw_cc_inprogress()
{
    if((MF_DCR(a_dsr) & DECOD_AUD_DSR_CHAN_CH) != 0)
    {
        return 1;
    }
    return 0;
}

void xp_atom_a_hw_sync_off()
{
    ULONG reg;

    reg = MF_DCR(a_ctrl0) & (~DECOD_AUD_CTRL0_ENABLE_SYNC);
    MT_DCR(a_ctrl0,reg);
}

void xp_atom_a_hw_sync_on()
{
    ULONG reg;

    reg = MF_DCR(a_ctrl0) | DECOD_AUD_CTRL0_ENABLE_SYNC;
    MT_DCR(a_ctrl0,reg);
}


void xp_atom_v_hw_sync_off()
{
    ULONG reg;

    reg = MF_DCR(v_c_cntl) |DECOD_CHIP_CONTROL_DIS_SYNC;
    MT_DCR(v_c_cntl,reg);
}

void xp_atom_v_hw_sync_on()
{
    ULONG reg;

    reg = MF_DCR(v_c_cntl) & (~DECOD_CHIP_CONTROL_DIS_SYNC);
    MT_DCR(v_c_cntl,reg);
}


int xp_atom_a_hw_write_stc(stc_t *data)
{
    unsigned long value;
    if((MF_DCR(a_dsr) & DECOD_AUD_DSR_COMMAND_COM) != 0)
        return -1;

    value = (data->bit_0|((data->bits_32_1<<1)&0x0000fffe));
    MT_DCR(a_stc,value);
    value = ((data->bits_32_1>>15) & (0x0000ffff));
    MT_DCR(a_stc,value);
    value = ((data->bits_32_1>>31) & (0x000000001));
    MT_DCR(a_stc,value);
    return 0;
}

int xp_atom_v_hw_write_stc(stc_t *data)
{
    unsigned long value;

    value = data->bit_0<<9;
    MT_DCR(v_s_stc1,value);
    value = data->bits_32_1;
    MT_DCR(v_s_stc0,value);

    return 0;
}