xp_osi.c

IBM source for pallas/vulcan/vesta

    xp_atom_dcr_write(pGlobal->uDeviceIndex,XP_DCR_ADDR_PLBCNFG,   0x00030010);
    xp_atom_dcr_write(pGlobal->uDeviceIndex,XP_DCR_ADDR_QSTATMASK, 0);

    for(i=0; i < XP_CHANNEL_COUNT; i++) {
      xp_atom_dcr_reset_queue(pGlobal->uDeviceIndex,i);
    }

    os_leave_critical_section(flag);

    /*-----------------------------------------------------------------------+
    |  Configure XP Registers
    +------------------------------------------------------------------------*/

    trans_set_configure(pGlobal);
    return(0);
}

/*----------------------------------------------------------------------------+
| XXXXXXX  XXX XXX   XXXXXX  XXXXXXX  XXXXXX   XX   XX     XX    XXXX
|  XX   X   XX XX    X XX X   XX   X   XX  XX  XXX  XX    XXXX    XX
|  XX X      XXX       XX     XX X     XX  XX  XXXX XX   XX  XX   XX
|  XXXX       X        XX     XXXX     XXXXX   XX XXXX   XX  XX   XX
|  XX X      XXX       XX     XX X     XX XX   XX  XXX   XXXXXX   XX
|  XX   X   XX XX      XX     XX   X   XX  XX  XX   XX   XX  XX   XX  XX
| XXXXXXX  XXX XXX    XXXX   XXXXXXX  XXX  XX  XX   XX   XX  XX  XXXXXXX
+----------------------------------------------------------------------------*/

/*----------------------------------------------------------------------------+
|   XX     XXXXXX    XXXXXX    XXXXX
|  XXXX    XX   XX     XX     XX   XX
| XX  XX   XX   XX     XX      XX
| XX  XX   XXXXX       XX        XX
| XXXXXX   XX          XX         XX
| XX  XX   XX          XX     XX   XX
| XX  XX   XX        XXXXXX    XXXXX
+----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------+
|  xp0_init
+----------------------------------------------------------------------------*/
short xp_osi_init(GLOBAL_RESOURCES *pGlobal)            /* memory available for DRAM queues     */
{
    short rc = 0;

    PDEBUG("Entering into xp_os_init\n");

    os_disable_irq(XP_IRQ);

    rc = trans_reset(pGlobal);

    if(rc == 0)
    {
      rc = xp_osi_interrupt_init(pGlobal);
    }

    if(rc == 0)
    {
      rc = xp_osi_channel_init(pGlobal);
    }

    if(rc == 0)
    {
      rc = xp_osi_queue_init(pGlobal);
    }

    if(rc == 0)
    {
      rc = xp_osi_filter_init(pGlobal);
    }

    if(rc == 0)
    {
      os_enable_irq(XP_IRQ);
    }

    if(pGlobal->uDeviceIndex == 0)
    {
      xp_osi_pcr_delay((45000/1000) * 60 * -1);
      if(rc == 0)
      {
        rc = xp_osi_clk_init(pGlobal);
      }
      PDEBUG("After xp_osi_clk_init(pGlobal), rc = %d\n",rc);
      if(rc == 0)
      {
        rc = xp_osi_clk_start(pGlobal);
      }
      if(rc == 0)
      {
        rc = xp_osi_cchan_init(pGlobal);
      }
      if(rc == 0)
      {
        rc = xp_osi_pcr_init(pGlobal);
      }
    }


    return(rc);

}

/*----------------------------------------------------------------------------+
|  xp0_get_config_values
+----------------------------------------------------------------------------*/
void xp_osi_get_config_values (GLOBAL_RESOURCES *pGlobal,XP_CONFIG_VALUES *configv_parm)
{

    XP_CONFIG_VALUES   *pXpConfigv = NULL;


    trans_get_configure(pGlobal);

    switch(pGlobal->uDeviceIndex)
    {
      case 0:
        pXpConfigv = &xp0_configv;
        break;
      case 1:
        pXpConfigv = &xp1_configv;
        break;
      case 2:
        pXpConfigv = &xp2_configv;
        break;
      default:
        break;
    }

    memcpy(configv_parm, pXpConfigv, sizeof(XP_CONFIG_VALUES));
}

/*----------------------------------------------------------------------------+
|  xp0_set_config_values
+----------------------------------------------------------------------------*/
void xp_osi_set_config_values (GLOBAL_RESOURCES *pGlobal, XP_CONFIG_VALUES *configv_parm)
{
    XP_CONFIG_VALUES   *pXpConfigv = NULL;


    switch(pGlobal->uDeviceIndex)
    {
      case 0:
        pXpConfigv = &xp0_configv;
        break;
      case 1:
        pXpConfigv = &xp1_configv;
        break;
      case 2:
        pXpConfigv = &xp2_configv;
        break;
      default:
        break;
    }

    memcpy(pXpConfigv, configv_parm, sizeof(XP_CONFIG_VALUES));
    trans_set_configure(pGlobal);
}


//The following 3 function are added by lingh for TS recoder
/*----------------------------------------------------------------------------+
|  xp0_osi_set_parse_bypass_mode
+----------------------------------------------------------------------------*/
void xp_osi_set_parse_bypass_mode(GLOBAL_RESOURCES *pGlobal)
{
    short             i = 0;
    XP_CONTROL1_REG   control1;
    int               j;
    UINT32            flag;
    ULONG             reg;
    int rc = 0;

    /*------------------------------------------------------------------------+
    |  Soft Reset Transport
    +------------------------------------------------------------------------*/
    memset(&control1, 0, sizeof(control1));
    control1.swrst = 1;

    flag = os_enter_critical_section();
    xp_atom_dcr_write(pGlobal->uDeviceIndex,XP_DCR_ADDR_CONTROL1, *(unsigned *)(void *)&control1);
    while (xp_atom_dcr_read(pGlobal->uDeviceIndex, XP_DCR_ADDR_CONTROL1) != 0)
    {
      for(j=0;j<1000000;j++)
        ;

      if (++i > 200)
      {
        os_leave_critical_section(flag);
        return;
      }
    }
    control1.swrst = 0;

    if(rc == 0)
    {
      xp_osi_queue_de_init(pGlobal);
      rc = xp_osi_queue_init(pGlobal);
    }


    PDEBUG("After xp_osi_queue_init(pGlobal), rc= %d\n",rc);

    if(rc == 0)
    {
      rc = xp_osi_filter_init(pGlobal);
    }

    reg = xp_atom_dcr_read(pGlobal->uDeviceIndex, XP_DCR_ADDR_INTMASK) & 0xc9c3ffff;
    xp_atom_dcr_write(pGlobal->uDeviceIndex, XP_DCR_ADDR_INTMASK, reg);
    reg = xp_atom_dcr_read(pGlobal->uDeviceIndex, XP_DCR_ADDR_QSTATMASK) & 0x0000e200;
    xp_atom_dcr_write(pGlobal->uDeviceIndex, XP_DCR_ADDR_QSTATMASK, reg);
    reg = xp_atom_dcr_read(pGlobal->uDeviceIndex, XP_DCR_ADDR_FEIMASK) & 0x00006ff7;
    xp_atom_dcr_write(pGlobal->uDeviceIndex, XP_DCR_ADDR_FEIMASK, reg);
    os_leave_critical_section(flag);
}

/*----------------------------------------------------------------------------+
|  xp0_osi_start_parse_bypass
+----------------------------------------------------------------------------*/
void xp_osi_start_parse_bypass(GLOBAL_RESOURCES *pGlobal)
{
    XP_CONTROL1_REG    control1;
    UINT32             flag;
    ULONG              reg;

    flag = os_enter_critical_section();
    reg = xp_atom_dcr_read(pGlobal->uDeviceIndex, XP_DCR_ADDR_CONTROL1);
    control1 = *(XP_CONTROL1_REG *)(void *)&reg;
    ulSavedCtlReg = reg;
    control1.pbe = 1;
    control1.senbl = 1;
    xp_atom_dcr_write(pGlobal->uDeviceIndex, XP_DCR_ADDR_CONTROL1, *(unsigned *)(void *)&control1);
    os_leave_critical_section(flag);
}

/*----------------------------------------------------------------------------+
|  xp0_osi_stop_parse_bypass
+----------------------------------------------------------------------------*/
void xp_osi_stop_parse_bypass(GLOBAL_RESOURCES *pGlobal)
{
    XP_CONTROL1_REG    control1;
    UINT32             flag;

    flag = os_enter_critical_section();
    control1 = *(XP_CONTROL1_REG*)(void *)&ulSavedCtlReg;

    xp_atom_dcr_write(pGlobal->uDeviceIndex, XP_DCR_ADDR_CONTROL1, *(unsigned *)(void *)&control1);
    os_leave_critical_section(flag);
}