xp_osi.c

IBM source for pallas/vulcan/vesta

          pXpConfigv = &xp1_configv;
          break;
      case 2:
          pXpConfigv = &xp2_configv;
          break;
      default:
          break;
    }

    /*-----------------------------------------------------------------------+
    |  Read Registers
    +------------------------------------------------------------------------*/
    flag = os_enter_critical_section();
    *(unsigned *)(void *)&config1  = xp_atom_dcr_read(pGlobal->uDeviceIndex,XP_DCR_ADDR_CONFIG1);
    *(unsigned *)(void *)&config2  = xp_atom_dcr_read(pGlobal->uDeviceIndex,XP_DCR_ADDR_CONFIG2);
#ifndef __DRV_FOR_VESTA__
    *(unsigned *)(void *)&config3  = xp_atom_dcr_read(pGlobal->uDeviceIndex,XP_DCR_ADDR_CONFIG3);
#endif
    *(unsigned *)(void *)&control1 = xp_atom_dcr_read(pGlobal->uDeviceIndex,XP_DCR_ADDR_CONTROL1);
    *(unsigned *)(void *)&pbuflvl  = xp_atom_dcr_read(pGlobal->uDeviceIndex,XP_DCR_ADDR_PBUFLVL);
    os_leave_critical_section(flag);

    /*-----------------------------------------------------------------------+
    |  Set Registers According to Stored Settings
    +------------------------------------------------------------------------*/
    pXpConfigv->vpu     = config1.vpu;
    pXpConfigv->apu     = config1.apu;
    pXpConfigv->tstoe   = config1.tstoe;
    pXpConfigv->tsclkp  = config1.tsclkp;
    pXpConfigv->tsdp    = config1.tsdp;
#ifdef __DRV_FOR_PALLAS__
    pXpConfigv->tssp    = config1.tssp;
    pXpConfigv->tsep    = config1.tsep;
    pXpConfigv->tssm    = config1.tssm;
#endif
    pXpConfigv->tsvp    = config1.tsvp;
    pXpConfigv->syncd   = config1.syncd;
    pXpConfigv->bbmode  = config1.bbmode;
    pXpConfigv->syncl   = config1.syncl;

    pXpConfigv->ved     = config2.ved;
    pXpConfigv->acpm    = config2.acpm;
    pXpConfigv->vcpm    = config2.vcpm;
    pXpConfigv->mwe     = config2.mwe;
    pXpConfigv->salign  = config2.salign;
    pXpConfigv->atsed   = config2.atsed;
    pXpConfigv->atbd    = config2.atbd;
    pXpConfigv->accd    = config2.accd;
    pXpConfigv->vtsed   = config2.vtsed;
    pXpConfigv->vtbd    = config2.vtbd;
    pXpConfigv->vccd    = config2.vccd;

#ifndef __DRV_FOR_VESTA__
    pXpConfigv->insel   = config3.insel;
#endif

    pXpConfigv->sbe     = control1.sbe;
    pXpConfigv->pbe     = control1.pbe;
    pXpConfigv->sdop    = control1.sdop;

    pXpConfigv->qpthres = pbuflvl.qpthres;
    pXpConfigv->apthres = pbuflvl.apthres;
    pXpConfigv->vpthres = pbuflvl.vpthres;

}

/*----------------------------------------------------------------------------+
|  trans_set_configure
+----------------------------------------------------------------------------*/
static void trans_set_configure(GLOBAL_RESOURCES *pGlobal)
{
    XP_CONFIG1_REG     config1;
    XP_CONFIG2_REG     config2;
#ifndef __DRV_FOR_VESTA__
    XP_CONFIG3_REG     config3;
#endif
    XP_CONTROL1_REG    control1;
    XP_PBUFLVL_REG     pbuflvl;
    XP_CONFIG_VALUES   *pXpConfigv = NULL;
    UINT32         flag;


    /*-----------------------------------------------------------------------+
    |  Get Configuration Values for specified Transport
    +------------------------------------------------------------------------*/
    switch(pGlobal->uDeviceIndex)
    {
      case 0:
          pXpConfigv = &xp0_configv;
          break;
      case 1:
          pXpConfigv = &xp1_configv;
          break;
      case 2:
          pXpConfigv = &xp2_configv;
          break;
      default:
          break;
    }

    /*-----------------------------------------------------------------------+
    |  Read Registers
    +------------------------------------------------------------------------*/
    flag = os_enter_critical_section();
    *(unsigned *)(void *)&config1  = xp_atom_dcr_read(pGlobal->uDeviceIndex,XP_DCR_ADDR_CONFIG1);
    *(unsigned *)(void *)&config2  = xp_atom_dcr_read(pGlobal->uDeviceIndex,XP_DCR_ADDR_CONFIG2);
#ifndef __DRV_FOR_VESTA__
    *(unsigned *)(void *)&config3  = xp_atom_dcr_read(pGlobal->uDeviceIndex,XP_DCR_ADDR_CONFIG3);
#endif
    *(unsigned *)(void *)&control1 = xp_atom_dcr_read(pGlobal->uDeviceIndex,XP_DCR_ADDR_CONTROL1);
    *(unsigned *)(void *)&pbuflvl  = xp_atom_dcr_read(pGlobal->uDeviceIndex,XP_DCR_ADDR_PBUFLVL);
    os_leave_critical_section(flag);

    /*-----------------------------------------------------------------------+
    |  Set Registers According to Stored Settings
    +------------------------------------------------------------------------*/
    config1.vpu      = pXpConfigv->vpu;
    config1.apu      = pXpConfigv->apu;
    config1.tstoe    = pXpConfigv->tstoe;
    config1.tsclkp   = pXpConfigv->tsclkp;
    config1.tsdp     = pXpConfigv->tsdp;
#ifdef __DRV_FOR_PALLAS__
    config1.tssp     = pXpConfigv->tssp;
    config1.tsep     = pXpConfigv->tsep;
    config1.tssm     = pXpConfigv->tssm;
#endif
    config1.tsvp     = pXpConfigv->tsvp;
    config1.syncd    = pXpConfigv->syncd;
    config1.bbmode   = pXpConfigv->bbmode;
    config1.syncl    = pXpConfigv->syncl;

    config2.ved      = pXpConfigv->ved;
    config2.acpm     = pXpConfigv->acpm;
    config2.vcpm     = pXpConfigv->vcpm;
    config2.mwe      = pXpConfigv->mwe;
    config2.salign   = pXpConfigv->salign;
    config2.atsed    = pXpConfigv->atsed;
    config2.atbd     = pXpConfigv->atbd;
    config2.accd     = pXpConfigv->accd;
    config2.vtsed    = pXpConfigv->vtsed;
    config2.vtbd     = pXpConfigv->vtbd;
    config2.vccd     = pXpConfigv->vccd;

#ifndef __DRV_FOR_VESTA__
    config3.insel    = pXpConfigv->insel;
#endif

    control1.sbe     = pXpConfigv->sbe;
    control1.pbe     = pXpConfigv->pbe;
    control1.sdop    = pXpConfigv->sdop;

    pbuflvl.qpthres  = pXpConfigv->qpthres;
    pbuflvl.apthres  = pXpConfigv->apthres;
    pbuflvl.vpthres  = pXpConfigv->vpthres;

    /*-----------------------------------------------------------------------+
    |  Write Registers with Control 1 Register, Bit SE, Set to 0
    +------------------------------------------------------------------------*/
    control1.senbl   = 0;
    flag = os_enter_critical_section();
    xp_atom_dcr_write(pGlobal->uDeviceIndex,XP_DCR_ADDR_CONFIG1,  *(unsigned *)(void *)&config1);
    xp_atom_dcr_write(pGlobal->uDeviceIndex,XP_DCR_ADDR_CONFIG2,  *(unsigned *)(void *)&config2);
#ifndef __DRV_FOR_VESTA__
    xp_atom_dcr_write(pGlobal->uDeviceIndex,XP_DCR_ADDR_CONFIG3,  *(unsigned *)(void *)&config3);
#endif
    xp_atom_dcr_write(pGlobal->uDeviceIndex,XP_DCR_ADDR_CONTROL1, *(unsigned *)(void *)&control1);
    xp_atom_dcr_write(pGlobal->uDeviceIndex,XP_DCR_ADDR_PBUFLVL,  *(unsigned *)(void *)&pbuflvl);
    os_leave_critical_section(flag);

    /*-----------------------------------------------------------------------+
    |  Set Control 1 Register, Bit SE, According to Settings
    +------------------------------------------------------------------------*/
    control1.senbl   = pXpConfigv->senbl;
    flag = os_enter_critical_section();
    xp_atom_dcr_write(pGlobal->uDeviceIndex,XP_DCR_ADDR_CONTROL1, *(unsigned *)(void *)&control1);
    os_leave_critical_section(flag);
}

/*----------------------------------------------------------------------------+
|  trans_reset
+----------------------------------------------------------------------------*/
static short trans_reset(GLOBAL_RESOURCES *pGlobal)
{

    short i = 0;
    int j;
    XP_CONTROL1_REG control1;
    UINT32 flag;

    /*------------------------------------------------------------------------+
    |  Init configuration vector to reset value
    +------------------------------------------------------------------------*/
    switch(pGlobal->uDeviceIndex)
    {

      case 0:
        memcpy(&xp0_configv, &xp0_configv_reset, sizeof(XP_CONFIG_VALUES));
        break;
      case 1:
        memcpy(&xp1_configv, &xp1_configv_reset, sizeof(XP_CONFIG_VALUES));
        break;
      case 2:
        memcpy(&xp2_configv, &xp2_configv_reset, sizeof(XP_CONFIG_VALUES));
        break;
      default:
        break;
    }

    /*------------------------------------------------------------------------+
    |  Soft Reset Transport
    +------------------------------------------------------------------------*/
    memset(&control1, 0, sizeof(control1));
    control1.swrst = 1;
    flag = os_enter_critical_section();
    xp_atom_dcr_write(pGlobal->uDeviceIndex,XP_DCR_ADDR_CONTROL1, *(unsigned *)(void *)&control1);

    while (xp_atom_dcr_read(pGlobal->uDeviceIndex, XP_DCR_ADDR_CONTROL1) != 0)
    {
      for(j=0;j<100000;j++)
        ;

      if (++i > 200)
      {
        os_leave_critical_section(flag);
        return(-1);
      }
    }

    /*-----------------------------------------------------------------------+
    |  Clear all registers that are at an unpredictable state after reset
    +------------------------------------------------------------------------*/
    xp_atom_dcr_write(pGlobal->uDeviceIndex,XP_DCR_ADDR_CONFIG1,   0);
    xp_atom_dcr_write(pGlobal->uDeviceIndex,XP_DCR_ADDR_CONTROL1,  0);
    xp_atom_dcr_write(pGlobal->uDeviceIndex,XP_DCR_ADDR_FEIMASK,   0);

#ifndef __DRV_FOR_VESTA__
    xp_atom_dcr_write(pGlobal->uDeviceIndex,XP_DCR_ADDR_CONFIG3,   0);
#endif

    xp_atom_dcr_write(pGlobal->uDeviceIndex,XP_DCR_ADDR_PCRSTCT,   0);
    xp_atom_dcr_write(pGlobal->uDeviceIndex,XP_DCR_ADDR_STCCOMP,   0);
    xp_atom_dcr_write(pGlobal->uDeviceIndex,XP_DCR_ADDR_DSIMASK,   0);

#ifndef __DRV_FOR_VULCAN__
    xp_atom_dcr_write(pGlobal->uDeviceIndex,XP_DCR_ADDR_AXENABLE,  0);
#endif

    xp_atom_dcr_write(pGlobal->uDeviceIndex,XP_DCR_ADDR_CONFIG2,   0);
    xp_atom_dcr_write(pGlobal->uDeviceIndex,XP_DCR_ADDR_PBUFLVL,   0);
    xp_atom_dcr_write(pGlobal->uDeviceIndex,XP_DCR_ADDR_INTMASK,   0);