vid_atom.c

IBM source for pallas/vulcan/vesta

void vid_atom_close()
{
    unsigned long reg;

    reg =
        MF_DCR(VID_CHIP_CTRL) &
        (~
         (DECOD_CHIP_CONTROL_SVP | 
          DECOD_CHIP_CONTROL_SVD |
          DECOD_CHIP_CONTROL_BLANK_VID));

    MT_DCR(VID_CHIP_CTRL, reg);
}


void vid_atom_set_dispmode(UINT uMode)
{
    unsigned long reg;

    reg = MF_DCR(VID_DISP_MODE) & 
          (~(
            DECOD_DISP_MODE_MASK|
            DECOD_DISP_MODE_16_9_MONITOR));
    //NTSC or PAL
    /*if(uMode & VID_MODE_PAL)
        reg |= DECOD_DISP_MODE_PAL_MODE;*/
    //4:3 or 16:9
    if(uMode & VID_MODE_16_9)
        reg |= DECOD_DISP_MODE_16_9_MONITOR;
    //display mode
    reg |= (uMode & 0x0f) << 1;
    MT_DCR(VID_DISP_MODE, reg);
    PDEBUG("set disp mode = 0x%lx\n", reg);
}

void vid_atom_set_dispfmt(UINT uPal)
{
    unsigned long reg;

    reg = MF_DCR(VID_DISP_MODE) & (~DECOD_DISP_MODE_PAL_MODE);
    if(uPal)
    {
        MT_DCR(VID_DISP_MODE, reg | DECOD_DISP_MODE_PAL_MODE);
        //get frame info in PAL mode
        vid_atom_set_fb_adr(1);
    }
    else
    {
        MT_DCR(VID_DISP_MODE, reg);
        //get frame info in NTSC mode
        vid_atom_set_fb_adr(0);
    }
    PDEBUG("set dispfmt = 0x%lx\n", reg);
}

void vid_atom_set_sfm(vidsfm_t sfm)
{
  unsigned reg;

  if(vid_sfm != VID_SFM_NORMAL)  /* if single field mode locked by the user */
    return;              /* ignore the request                      */
    
  reg = MF_DCR(VID_DISP_MODE) & ~DECOD_DISP_MODE_SFM_MASK;
  switch(sfm)
  {
    case VID_SFM_NORMAL:
        reg |= DECOD_DISP_MODE_NORM_DISP;
        break;
    case VID_SFM_BOTTOM_ONLY:
        reg |= DECOD_DISP_MODE_BOTTOM_ONLY;
        break;
    case VID_SFM_TOP_ONLY:
        reg |= DECOD_DISP_MODE_TOP_ONLY;
        break;
    case VID_SFM_FIRST_ONLY:
        reg |= DECOD_DISP_MODE_FIRST_ONLY;
        break;
  }

  MT_DCR(VID_DISP_MODE, reg);
  return;
}

void vid_atom_set_dispborder(UINT uLeft, UINT uTop)
{
    unsigned long reg;    

    PDEBUG("set disp border left = %d, top = %d\n", uLeft, uTop);

    uLeft &= 0x03ff;
    uTop  &= 0x03ff;
    reg = MF_DCR(VID_DISP_BOR);
    reg = reg | uLeft << 16 | uTop;
    MT_DCR(VID_DISP_BOR, reg);
}


void vid_atom_set_scalepos(RECT *prectSrc, RECT *prectDes)
{
    int x, y;

    PDEBUG("src hori off = 0x%8.8x, src hori size = 0x%8.8x\n", prectSrc->hori_off, prectSrc->hori_size);
    PDEBUG("src veri off = 0x%8.8x, src veri size = 0x%8.8x\n", prectSrc->vert_off, prectSrc->vert_size);
    PDEBUG("des hori off = 0x%8.8x, des hori size = 0x%8.8x\n", prectDes->hori_off, prectDes->hori_size);
    PDEBUG("des veri off = 0x%8.8x, des veri size = 0x%8.8x\n", prectDes->vert_off, prectDes->vert_size);

#ifdef __DRV_FOR_PALLAS__
    //CROP OFFSET
    //10bits horizontal offset to the center of the frame
    x =  (prectSrc->hori_off) & 0x03ff;     
    //10bits vertical offset to the center of the frame
    y =  (prectSrc->vert_off) & 0x03ff;     
    MT_DCR(VID_CROP_OFFSET, (x << 16) | y);

    //CROP SIZE
    x = (prectSrc->hori_size) & 0x03ff;
    y = (prectSrc->vert_size) & 0x03ff;
    MT_DCR(VID_CROP_SIZE, (x << 16) | y);
    
    //SCALE BORDER
    x = (prectDes->hori_off) & 0x03ff;     
    //10bits vertical offset to the center of the frame
    y = (prectDes->vert_off) & 0x03ff;     
    MT_DCR(VID_SCALE_BORDER, (x << 16) | y);
  
    //SCALE SIZE
    x = (prectDes->hori_size) & 0x03ff;     
    //10bits vertical offset to the center of the frame
    y = (prectDes->vert_size) & 0x03ff;     
    MT_DCR(VID_SCALE_SIZE, (x << 16) | y);
#else

	x = (prectDes->hori_off) & 0xff;
	y = (prectDes->vert_off) & 0xff;
	MT_DCR(VID_SMALL_BORDER, (x << 16) | y);
#endif
	return;
}


void vid_atom_scale_on(UINT uFlag)
{
#ifdef __DRV_FOR_PALLAS__
	unsigned long reg;
    reg = MF_DCR(VID_CROP_SIZE) & (~DECOD_CROP_SIZE_SS);

    if(uFlag)
    {
        reg |= DECOD_CROP_SIZE_SS;  //original size
    }
    MT_DCR(VID_CROP_SIZE, reg);

    reg = MF_DCR(VID_DISP_MODE) & (~DECOD_DISP_MODE_MASK);
    reg |= ( VID_MODE_SCALE << 1);
    MT_DCR(VID_DISP_MODE, reg);
#endif 
	return;
}

void vid_atom_scale_off()
{
    unsigned long reg;
    
    reg = MF_DCR(VID_DISP_MODE) & (~DECOD_DISP_MODE_MASK);
    MT_DCR(VID_DISP_MODE, reg);
}


UINT32  vid_atom_get_irq_mask()
{
    return MF_DCR(VID_MASK);
}

void vid_atom_set_irq_mask(UINT32 uMask)
{
    UINT32 flags;

    flags = os_enter_critical_section();
    vid_mask_save = uMask & DECOD_HOST_MASK_VBI_START;
    MT_DCR(VID_MASK, uMask);
    os_leave_critical_section(flags);
}

void vid_atom_init_irq_mask()
{
    UINT32 flags;
    
    flags = os_enter_critical_section();
    MT_DCR(VID_MASK, DEF_VID_IRQ_MASK | vid_mask_save);
    os_leave_critical_section(flags);
}


INT vid_atom_init_tv(AT_MEM *pRateBase, UINT uRateThreshold)
{
    unsigned long reg;

    if(pRateBase != NULL)
    {
        /*-------------------------------------------------------------------------
        | set rate buffer base and size
        +--------------------------------------------------------------------------*/
//        if((pRateBase->uAddr % DECOD_MEM_ALIGN) != 0)
        if((pRateBase->ulVideoLogicalAddr % DECOD_MEM_ALIGN) != 0)
            MT_DCR(VID_RB_BASE, pRateBase->uAddr / DECOD_MEM_ALIGN);
        if((pRateBase->uLen % DECOD_RB_ALIGN) != 0)
            MT_DCR(VID_RB_SIZE, pRateBase->uLen / DECOD_RB_ALIGN);
    }
    //rate buffer threshold to be done

    PDEBUG("start tv mode\n");

    reg = MF_DCR(VID_CHIP_CTRL);
    reg = reg & (~DECOD_CHIP_CONTROL_VID_CLIP);
    MT_DCR(VID_CHIP_CTRL, reg);

    return 0;
}


/*---------------------------------------------------------------------------+
| GET microcode version
+----------------------------------------------------------------------------*/
INT vid_atom_get_microcode_ver(ULONG *pVer)
{
   int   rc = 0;

   if (vid_ucode_len==1) {
     rc = -1;
   } else {
     *pVer = (ULONG)(vid_ucode[0]);
   }
   return(rc);
}


void vid_atom_blank()
{
    unsigned long reg;

    PDEBUG("video plane disable\n");
    reg = MF_DCR(VID_CHIP_CTRL);
    MT_DCR(VID_CHIP_CTRL, reg & (~DECOD_CHIP_CONTROL_BLANK_VID));

    return;
}

void vid_atom_show()
{
    unsigned long reg;

    PDEBUG("video plane enable\n");
    reg = MF_DCR(VID_CHIP_CTRL);
    MT_DCR(VID_CHIP_CTRL, reg | DECOD_CHIP_CONTROL_BLANK_VID);  /* enable vid */
    return;
}





void vid_atom_reg_dump()
{
    PDEBUG("CTRL = 0x%8x\n", MF_DCR(VID_CHIP_CTRL));
    PDEBUG("DISP MODE = 0x%8.8x\n", MF_DCR(VID_DISP_MODE));
    PDEBUG("DISP DLY = 0x%8.8x\n", MF_DCR(VID_DISP_DLY));
    PDEBUG("MEM SEG 0 = 0x%8.8x\n", MF_DCR(VID_SEG0));
    PDEBUG("MEM SEG 1 = 0x%8.8x\n", MF_DCR(VID_SEG1));
    PDEBUG("MEM SEG 2 = 0x%8.8x\n", MF_DCR(VID_SEG2));
    PDEBUG("MEM SEG 3 = 0x%8.8x\n", MF_DCR(VID_SEG3));
    PDEBUG("USER BUF = 0x%8.8x\n", MF_DCR(VID_USERDATA_BASE));
    PDEBUG("FRAME BUF = 0x%8.8x\n", MF_DCR(VID_FRAME_BUF));
    PDEBUG("RB BUF = 0x%8.8x\n", MF_DCR(VID_RB_BASE));
    PDEBUG("RB SIZE = 0x%8.8x\n", MF_DCR(VID_RB_SIZE));
}

//lingh added for PVR demo
void vid_atom_set_rb_size(ULONG value)
{
	MT_DCR(VID_RB_SIZE, value);
}
//lingh added for PVR demo
int vid_atom_single_frame(int mode)
{
    VIDEOCMD vc;
    int i;
    // set display to first field only
    vid_atom_set_sfm(VID_SFM_FIRST_ONLY); 
    
    vc.uCmd = DECOD_COM_SFRAME;
    vc.uNum = 1;
    vc.uPara[0] = mode;
    vc.uChained = 0;
    vc.uRetry = DECOD_TIMEOUT;

    if (vid_atom_exec_cmd(&vc) != 0)
    {
        return -1;
    }

    for(i = 0; i< 256; i++)
    {
        if(vid_atom_svd_has_reset() == 0)
	break;
		
	os_sleep(10);
    }

    if(i >= 256)
    {
	return -1;
    }

    return 0;
}

INT vid_atom_svd_has_reset()
{
	if((MF_DCR(VID_CHIP_CTRL) & 0x01) == 0)
		return 0;

	return -1;
}

int vid_atom_resume_from_sf(ULONG mode)
{
	int ret=0;

	if(mode == 0)
	{
		ret = vid_atom_reset_ratebuf(0xf000);
	}

	MT_DCR(VID_CHIP_CTRL, MF_DCR(VID_CHIP_CTRL) | 0x01);
	return ret;
}

INT vid_atom_force_frame_switch(ULONG initflag)
{
  VIDEOCMD vc;

  vc.uCmd = DECOD_COM_FRAME_SW;
  vc.uNum = 1;
  vc.uChained = 0;
  vc.uRetry = DECOD_TIMEOUT;
  vc.uPara[0] = initflag;

  if (vid_atom_exec_cmd(&vc) != 0)
  {
    return -1;
  }

  return(0);
}