ctrl.tan.qmsg

quarters2编写的定时器.vhd为源程序

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register lpm_counter:\\a:cnt\[0\]_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[0\] register displow\[1\] 103.09 MHz 9.7 ns Internal " "Info: Clock \"clk\" has Internal fmax of 103.09 MHz between source register \"lpm_counter:\\a:cnt\[0\]_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[0\]\" and destination register \"displow\[1\]\" (period= 9.7 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.600 ns + Longest register register " "Info: + Longest register to register delay is 8.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:\\a:cnt\[0\]_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[0\] 1 REG LC3_B34 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3_B34; Fanout = 3; REG Node = 'lpm_counter:\\a:cnt\[0\]_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[0\]'" {  } { { "D:/dingshi/db/ctrl_cmp.qrpt" "" { Report "D:/dingshi/db/ctrl_cmp.qrpt" Compiler "ctrl" "UNKNOWN" "V1" "D:/dingshi/db/ctrl.quartus_db" { Floorplan "D:/dingshi/" "" "" { lpm_counter:\a:cnt[0]_rtl_1|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.600 ns) 1.900 ns LessThan~168 2 COMB LC1_B34 1 " "Info: 2: + IC(0.300 ns) + CELL(1.600 ns) = 1.900 ns; Loc. = LC1_B34; Fanout = 1; COMB Node = 'LessThan~168'" {  } { { "D:/dingshi/db/ctrl_cmp.qrpt" "" { Report "D:/dingshi/db/ctrl_cmp.qrpt" Compiler "ctrl" "UNKNOWN" "V1" "D:/dingshi/db/ctrl.quartus_db" { Floorplan "D:/dingshi/" "" "1.900 ns" { lpm_counter:\a:cnt[0]_rtl_1|alt_counter_f10ke:wysi_counter|q[0] LessThan~168 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.900 ns) + CELL(1.400 ns) 4.200 ns LessThan~169 3 COMB LC1_B35 3 " "Info: 3: + IC(0.900 ns) + CELL(1.400 ns) = 4.200 ns; Loc. = LC1_B35; Fanout = 3; COMB Node = 'LessThan~169'" {  } { { "D:/dingshi/db/ctrl_cmp.qrpt" "" { Report "D:/dingshi/db/ctrl_cmp.qrpt" Compiler "ctrl" "UNKNOWN" "V1" "D:/dingshi/db/ctrl.quartus_db" { Floorplan "D:/dingshi/" "" "2.300 ns" { LessThan~168 LessThan~169 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.900 ns) + CELL(1.600 ns) 6.700 ns rtl~2 4 COMB LC1_B36 4 " "Info: 4: + IC(0.900 ns) + CELL(1.600 ns) = 6.700 ns; Loc. = LC1_B36; Fanout = 4; COMB Node = 'rtl~2'" {  } { { "D:/dingshi/db/ctrl_cmp.qrpt" "" { Report "D:/dingshi/db/ctrl_cmp.qrpt" Compiler "ctrl" "UNKNOWN" "V1" "D:/dingshi/db/ctrl.quartus_db" { Floorplan "D:/dingshi/" "" "2.500 ns" { LessThan~169 rtl~2 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.900 ns) + CELL(1.000 ns) 8.600 ns displow\[1\] 5 REG LC3_B35 10 " "Info: 5: + IC(0.900 ns) + CELL(1.000 ns) = 8.600 ns; Loc. = LC3_B35; Fanout = 10; REG Node = 'displow\[1\]'" {  } { { "D:/dingshi/db/ctrl_cmp.qrpt" "" { Report "D:/dingshi/db/ctrl_cmp.qrpt" Compiler "ctrl" "UNKNOWN" "V1" "D:/dingshi/db/ctrl.quartus_db" { Floorplan "D:/dingshi/" "" "1.900 ns" { rtl~2 displow[1] } "NODE_NAME" } "" } } { "ctrl.vhd" "" { Text "D:/dingshi/ctrl.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.600 ns 65.12 % " "Info: Total cell delay = 5.600 ns ( 65.12 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.000 ns 34.88 % " "Info: Total interconnect delay = 3.000 ns ( 34.88 % )" {  } {  } 0}  } { { "D:/dingshi/db/ctrl_cmp.qrpt" "" { Report "D:/dingshi/db/ctrl_cmp.qrpt" Compiler "ctrl" "UNKNOWN" "V1" "D:/dingshi/db/ctrl.quartus_db" { Floorplan "D:/dingshi/" "" "8.600 ns" { lpm_counter:\a:cnt[0]_rtl_1|alt_counter_f10ke:wysi_counter|q[0] LessThan~168 LessThan~169 rtl~2 displow[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "8.600 ns" { lpm_counter:\a:cnt[0]_rtl_1|alt_counter_f10ke:wysi_counter|q[0] LessThan~168 LessThan~169 rtl~2 displow[1] } { 0.000ns 0.300ns 0.900ns 0.900ns 0.900ns } { 0.000ns 1.600ns 1.400ns 1.600ns 1.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.400 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clk 1 CLK PIN_55 20 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 20; CLK Node = 'clk'" {  } { { "D:/dingshi/db/ctrl_cmp.qrpt" "" { Report "D:/dingshi/db/ctrl_cmp.qrpt" Compiler "ctrl" "UNKNOWN" "V1" "D:/dingshi/db/ctrl.quartus_db" { Floorplan "D:/dingshi/" "" "" { clk } "NODE_NAME" } "" } } { "ctrl.vhd" "" { Text "D:/dingshi/ctrl.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.000 ns) 2.400 ns displow\[1\] 2 REG LC3_B35 10 " "Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC3_B35; Fanout = 10; REG Node = 'displow\[1\]'" {  } { { "D:/dingshi/db/ctrl_cmp.qrpt" "" { Report "D:/dingshi/db/ctrl_cmp.qrpt" Compiler "ctrl" "UNKNOWN" "V1" "D:/dingshi/db/ctrl.quartus_db" { Floorplan "D:/dingshi/" "" "0.400 ns" { clk displow[1] } "NODE_NAME" } "" } } { "ctrl.vhd" "" { Text "D:/dingshi/ctrl.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns 83.33 % " "Info: Total cell delay = 2.000 ns ( 83.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns 16.67 % " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" {  } {  } 0}  } { { "D:/dingshi/db/ctrl_cmp.qrpt" "" { Report "D:/dingshi/db/ctrl_cmp.qrpt" Compiler "ctrl" "UNKNOWN" "V1" "D:/dingshi/db/ctrl.quartus_db" { Floorplan "D:/dingshi/" "" "2.400 ns" { clk displow[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.400 ns" { clk clk~out displow[1] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.400 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clk 1 CLK PIN_55 20 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 20; CLK Node = 'clk'" {  } { { "D:/dingshi/db/ctrl_cmp.qrpt" "" { Report "D:/dingshi/db/ctrl_cmp.qrpt" Compiler "ctrl" "UNKNOWN" "V1" "D:/dingshi/db/ctrl.quartus_db" { Floorplan "D:/dingshi/" "" "" { clk } "NODE_NAME" } "" } } { "ctrl.vhd" "" { Text "D:/dingshi/ctrl.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.000 ns) 2.400 ns lpm_counter:\\a:cnt\[0\]_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[0\] 2 REG LC3_B34 3 " "Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC3_B34; Fanout = 3; REG Node = 'lpm_counter:\\a:cnt\[0\]_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[0\]'" {  } { { "D:/dingshi/db/ctrl_cmp.qrpt" "" { Report "D:/dingshi/db/ctrl_cmp.qrpt" Compiler "ctrl" "UNKNOWN" "V1" "D:/dingshi/db/ctrl.quartus_db" { Floorplan "D:/dingshi/" "" "0.400 ns" { clk lpm_counter:\a:cnt[0]_rtl_1|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns 83.33 % " "Info: Total cell delay = 2.000 ns ( 83.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns 16.67 % " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" {  } {  } 0}  } { { "D:/dingshi/db/ctrl_cmp.qrpt" "" { Report "D:/dingshi/db/ctrl_cmp.qrpt" Compiler "ctrl" "UNKNOWN" "V1" "D:/dingshi/db/ctrl.quartus_db" { Floorplan "D:/dingshi/" "" "2.400 ns" { clk lpm_counter:\a:cnt[0]_rtl_1|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.400 ns" { clk clk~out lpm_counter:\a:cnt[0]_rtl_1|alt_counter_f10ke:wysi_counter|q[0] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } }  } 0}  } { { "D:/dingshi/db/ctrl_cmp.qrpt" "" { Report "D:/dingshi/db/ctrl_cmp.qrpt" Compiler "ctrl" "UNKNOWN" "V1" "D:/dingshi/db/ctrl.quartus_db" { Floorplan "D:/dingshi/" "" "2.400 ns" { clk displow[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.400 ns" { clk clk~out displow[1] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } } { "D:/dingshi/db/ctrl_cmp.qrpt" "" { Report "D:/dingshi/db/ctrl_cmp.qrpt" Compiler "ctrl" "UNKNOWN" "V1" "D:/dingshi/db/ctrl.quartus_db" { Floorplan "D:/dingshi/" "" "2.400 ns" { clk lpm_counter:\a:cnt[0]_rtl_1|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.400 ns" { clk clk~out lpm_counter:\a:cnt[0]_rtl_1|alt_counter_f10ke:wysi_counter|q[0] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.500 ns + " "Info: + Micro clock to output delay of source is 0.500 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.600 ns + " "Info: + Micro setup delay of destination is 0.600 ns" {  } { { "ctrl.vhd" "" { Text "D:/dingshi/ctrl.vhd" 10 -1 0 } }  } 0}  } { { "D:/dingshi/db/ctrl_cmp.qrpt" "" { Report "D:/dingshi/db/ctrl_cmp.qrpt" Compiler "ctrl" "UNKNOWN" "V1" "D:/dingshi/db/ctrl.quartus_db" { Floorplan "D:/dingshi/" "" "8.600 ns" { lpm_counter:\a:cnt[0]_rtl_1|alt_counter_f10ke:wysi_counter|q[0] LessThan~168 LessThan~169 rtl~2 displow[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "8.600 ns" { lpm_counter:\a:cnt[0]_rtl_1|alt_counter_f10ke:wysi_counter|q[0] LessThan~168 LessThan~169 rtl~2 displow[1] } { 0.000ns 0.300ns 0.900ns 0.900ns 0.900ns } { 0.000ns 1.600ns 1.400ns 1.600ns 1.000ns } } } { "D:/dingshi/db/ctrl_cmp.qrpt" "" { Report "D:/dingshi/db/ctrl_cmp.qrpt" Compiler "ctrl" "UNKNOWN" "V1" "D:/dingshi/db/ctrl.quartus_db" { Floorplan "D:/dingshi/" "" "2.400 ns" { clk displow[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.400 ns" { clk clk~out displow[1] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } } { "D:/dingshi/db/ctrl_cmp.qrpt" "" { Report "D:/dingshi/db/ctrl_cmp.qrpt" Compiler "ctrl" "UNKNOWN" "V1" "D:/dingshi/db/ctrl.quartus_db" { Floorplan "D:/dingshi/" "" "2.400 ns" { clk lpm_counter:\a:cnt[0]_rtl_1|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.400 ns" { clk clk~out lpm_counter:\a:cnt[0]_rtl_1|alt_counter_f10ke:wysi_counter|q[0] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "displow\[0\] cn clk 5.600 ns register " "Info: tsu for register \"displow\[0\]\" (data pin = \"cn\", clock pin = \"clk\") is 5.600 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.400 ns + Longest pin register " "Info: + Longest pin to register delay is 7.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns cn 1 PIN PIN_124 11 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_124; Fanout = 11; PIN Node = 'cn'" {  } { { "D:/dingshi/db/ctrl_cmp.qrpt" "" { Report "D:/dingshi/db/ctrl_cmp.qrpt" Compiler "ctrl" "UNKNOWN" "V1" "D:/dingshi/db/ctrl.quartus_db" { Floorplan "D:/dingshi/" "" "" { cn } "NODE_NAME" } "" } } { "ctrl.vhd" "" { Text "D:/dingshi/ctrl.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.400 ns) 3.700 ns lpm_counter:disphigh_rtl_0\|alt_counter_f10ke:wysi_counter\|counter_cell\[3\]~177 2 COMB LC1_B33 9 " "Info: 2: + IC(0.300 ns) + CELL(1.400 ns) = 3.700 ns; Loc. = LC1_B33; Fanout = 9; COMB Node = 'lpm_counter:disphigh_rtl_0\|alt_counter_f10ke:wysi_counter\|counter_cell\[3\]~177'" {  } { { "D:/dingshi/db/ctrl_cmp.qrpt" "" { Report "D:/dingshi/db/ctrl_cmp.qrpt" Compiler "ctrl" "UNKNOWN" "V1" "D:/dingshi/db/ctrl.quartus_db" { Floorplan "D:/dingshi/" "" "1.700 ns" { cn lpm_counter:disphigh_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]~177 } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 311 15 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(1.600 ns) 6.300 ns rtl~761 3 COMB LC5_B35 1 " "Info: 3: + IC(1.000 ns) + CELL(1.600 ns) = 6.300 ns; Loc. = LC5_B35; Fanout = 1; COMB Node = 'rtl~761'" {  } { { "D:/dingshi/db/ctrl_cmp.qrpt" "" { Report "D:/dingshi/db/ctrl_cmp.qrpt" Compiler "ctrl" "UNKNOWN" "V1" "D:/dingshi/db/ctrl.quartus_db" { Floorplan "D:/dingshi/" "" "2.600 ns" { lpm_counter:disphigh_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]~177 rtl~761 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(0.800 ns) 7.400 ns displow\[0\] 4 REG LC7_B35 9 " "Info: 4: + IC(0.300 ns) + CELL(0.800 ns) = 7.400 ns; Loc. = LC7_B35; Fanout = 9; REG Node = 'displow\[0\]'" {  } { { "D:/dingshi/db/ctrl_cmp.qrpt" "" { Report "D:/dingshi/db/ctrl_cmp.qrpt" Compiler "ctrl" "UNKNOWN" "V1" "D:/dingshi/db/ctrl.quartus_db" { Floorplan "D:/dingshi/" "" "1.100 ns" { rtl~761 displow[0] } "NODE_NAME" } "" } } { "ctrl.vhd" "" { Text "D:/dingshi/ctrl.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.800 ns 78.38 % " "Info: Total cell delay = 5.800 ns ( 78.38 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.600 ns 21.62 % " "Info: Total interconnect delay = 1.600 ns ( 21.62 % )" {  } {  } 0}  } { { "D:/dingshi/db/ctrl_cmp.qrpt" "" { Report "D:/dingshi/db/ctrl_cmp.qrpt" Compiler "ctrl" "UNKNOWN" "V1" "D:/dingshi/db/ctrl.quartus_db" { Floorplan "D:/dingshi/" "" "7.400 ns" { cn lpm_counter:disphigh_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]~177 rtl~761 displow[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "7.400 ns" { cn cn~out lpm_counter:disphigh_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]~177 rtl~761 displow[0] } { 0.000ns 0.000ns 0.300ns 1.000ns 0.300ns } { 0.000ns 2.000ns 1.400ns 1.600ns 0.800ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.600 ns + " "Info: + Micro setup delay of destination is 0.600 ns" {  } { { "ctrl.vhd" "" { Text "D:/dingshi/ctrl.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.400 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clk 1 CLK PIN_55 20 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 20; CLK Node = 'clk'" {  } { { "D:/dingshi/db/ctrl_cmp.qrpt" "" { Report "D:/dingshi/db/ctrl_cmp.qrpt" Compiler "ctrl" "UNKNOWN" "V1" "D:/dingshi/db/ctrl.quartus_db" { Floorplan "D:/dingshi/" "" "" { clk } "NODE_NAME" } "" } } { "ctrl.vhd" "" { Text "D:/dingshi/ctrl.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.000 ns) 2.400 ns displow\[0\] 2 REG LC7_B35 9 " "Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC7_B35; Fanout = 9; REG Node = 'displow\[0\]'" {  } { { "D:/dingshi/db/ctrl_cmp.qrpt" "" { Report "D:/dingshi/db/ctrl_cmp.qrpt" Compiler "ctrl" "UNKNOWN" "V1" "D:/dingshi/db/ctrl.quartus_db" { Floorplan "D:/dingshi/" "" "0.400 ns" { clk displow[0] } "NODE_NAME" } "" } } { "ctrl.vhd" "" { Text "D:/dingshi/ctrl.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns 83.33 % " "Info: Total cell delay = 2.000 ns ( 83.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns 16.67 % " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" {  } {  } 0}  } { { "D:/dingshi/db/ctrl_cmp.qrpt" "" { Report "D:/dingshi/db/ctrl_cmp.qrpt" Compiler "ctrl" "UNKNOWN" "V1" "D:/dingshi/db/ctrl.quartus_db" { Floorplan "D:/dingshi/" "" "2.400 ns" { clk displow[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.400 ns" { clk clk~out displow[0] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } }  } 0}  } { { "D:/dingshi/db/ctrl_cmp.qrpt" "" { Report "D:/dingshi/db/ctrl_cmp.qrpt" Compiler "ctrl" "UNKNOWN" "V1" "D:/dingshi/db/ctrl.quartus_db" { Floorplan "D:/dingshi/" "" "7.400 ns" { cn lpm_counter:disphigh_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]~177 rtl~761 displow[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "7.400 ns" { cn cn~out lpm_counter:disphigh_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]~177 rtl~761 displow[0] } { 0.000ns 0.000ns 0.300ns 1.000ns 0.300ns } { 0.000ns 2.000ns 1.400ns 1.600ns 0.800ns } } } { "D:/dingshi/db/ctrl_cmp.qrpt" "" { Report "D:/dingshi/db/ctrl_cmp.qrpt" Compiler "ctrl" "UNKNOWN" "V1" "D:/dingshi/db/ctrl.quartus_db" { Floorplan "D:/dingshi/" "" "2.400 ns" { clk displow[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.400 ns" { clk clk~out displow[0] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk low\[1\] displow\[1\] 11.500 ns register " "Info: tco from clock \"clk\" to destination pin \"low\[1\]\" through register \"displow\[1\]\" is 11.500 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.400 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clk 1 CLK PIN_55 20 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 20; CLK Node = 'clk'" {  } { { "D:/dingshi/db/ctrl_cmp.qrpt" "" { Report "D:/dingshi/db/ctrl_cmp.qrpt" Compiler "ctrl" "UNKNOWN" "V1" "D:/dingshi/db/ctrl.quartus_db" { Floorplan "D:/dingshi/" "" "" { clk } "NODE_NAME" } "" } } { "ctrl.vhd" "" { Text "D:/dingshi/ctrl.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.000 ns) 2.400 ns displow\[1\] 2 REG LC3_B35 10 " "Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC3_B35; Fanout = 10; REG Node = 'displow\[1\]'" {  } { { "D:/dingshi/db/ctrl_cmp.qrpt" "" { Report "D:/dingshi/db/ctrl_cmp.qrpt" Compiler "ctrl" "UNKNOWN" "V1" "D:/dingshi/db/ctrl.quartus_db" { Floorplan "D:/dingshi/" "" "0.400 ns" { clk displow[1] } "NODE_NAME" } "" } } { "ctrl.vhd" "" { Text "D:/dingshi/ctrl.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns 83.33 % " "Info: Total cell delay = 2.000 ns ( 83.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns 16.67 % " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" {  } {  } 0}  } { { "D:/dingshi/db/ctrl_cmp.qrpt" "" { Report "D:/dingshi/db/ctrl_cmp.qrpt" Compiler "ctrl" "UNKNOWN" "V1" "D:/dingshi/db/ctrl.quartus_db" { Floorplan "D:/dingshi/" "" "2.400 ns" { clk displow[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.400 ns" { clk clk~out displow[1] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.500 ns + " "Info: + Micro clock to output delay of source is 0.500 ns" {  } { { "ctrl.vhd" "" { Text "D:/dingshi/ctrl.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.600 ns + Longest register pin " "Info: + Longest register to pin delay is 8.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns displow\[1\] 1 REG LC3_B35 10 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3_B35; Fanout = 10; REG Node = 'displow\[1\]'" {  } { { "D:/dingshi/db/ctrl_cmp.qrpt" "" { Report "D:/dingshi/db/ctrl_cmp.qrpt" Compiler "ctrl" "UNKNOWN" "V1" "D:/dingshi/db/ctrl.quartus_db" { Floorplan "D:/dingshi/" "" "" { displow[1] } "NODE_NAME" } "" } } { "ctrl.vhd" "" { Text "D:/dingshi/ctrl.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.300 ns) + CELL(6.300 ns) 8.600 ns low\[1\] 2 PIN PIN_99 0 " "Info: 2: + IC(2.300 ns) + CELL(6.300 ns) = 8.600 ns; Loc. = PIN_99; Fanout = 0; PIN Node = 'low\[1\]'" {  } { { "D:/dingshi/db/ctrl_cmp.qrpt" "" { Report "D:/dingshi/db/ctrl_cmp.qrpt" Compiler "ctrl" "UNKNOWN" "V1" "D:/dingshi/db/ctrl.quartus_db" { Floorplan "D:/dingshi/" "" "8.600 ns" { displow[1] low[1] } "NODE_NAME" } "" } } { "ctrl.vhd" "" { Text "D:/dingshi/ctrl.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.300 ns 73.26 % " "Info: Total cell delay = 6.300 ns ( 73.26 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.300 ns 26.74 % " "Info: Total interconnect delay = 2.300 ns ( 26.74 % )" {  } {  } 0}  } { { "D:/dingshi/db/ctrl_cmp.qrpt" "" { Report "D:/dingshi/db/ctrl_cmp.qrpt" Compiler "ctrl" "UNKNOWN" "V1" "D:/dingshi/db/ctrl.quartus_db" { Floorplan "D:/dingshi/" "" "8.600 ns" { displow[1] low[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "8.600 ns" { displow[1] low[1] } { 0.000ns 2.300ns } { 0.000ns 6.300ns } } }  } 0}  } { { "D:/dingshi/db/ctrl_cmp.qrpt" "" { Report "D:/dingshi/db/ctrl_cmp.qrpt" Compiler "ctrl" "UNKNOWN" "V1" "D:/dingshi/db/ctrl.quartus_db" { Floorplan "D:/dingshi/" "" "2.400 ns" { clk displow[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.400 ns" { clk clk~out displow[1] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } } { "D:/dingshi/db/ctrl_cmp.qrpt" "" { Report "D:/dingshi/db/ctrl_cmp.qrpt" Compiler "ctrl" "UNKNOWN" "V1" "D:/dingshi/db/ctrl.quartus_db" { Floorplan "D:/dingshi/" "" "8.600 ns" { displow[1] low[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "8.600 ns" { displow[1] low[1] } { 0.000ns 2.300ns } { 0.000ns 6.300ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "displow\[3\] cn clk -1.000 ns register " "Info: th for register \"displow\[3\]\" (data pin = \"cn\", clock pin = \"clk\") is -1.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.400 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clk 1 CLK PIN_55 20 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 20; CLK Node = 'clk'" {  } { { "D:/dingshi/db/ctrl_cmp.qrpt" "" { Report "D:/dingshi/db/ctrl_cmp.qrpt" Compiler "ctrl" "UNKNOWN" "V1" "D:/dingshi/db/ctrl.quartus_db" { Floorplan "D:/dingshi/" "" "" { clk } "NODE_NAME" } "" } } { "ctrl.vhd" "" { Text "D:/dingshi/ctrl.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.000 ns) 2.400 ns displow\[3\] 2 REG LC6_B36 8 " "Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC6_B36; Fanout = 8; REG Node = 'displow\[3\]'" {  } { { "D:/dingshi/db/ctrl_cmp.qrpt" "" { Report "D:/dingshi/db/ctrl_cmp.qrpt" Compiler "ctrl" "UNKNOWN" "V1" "D:/dingshi/db/ctrl.quartus_db" { Floorplan "D:/dingshi/" "" "0.400 ns" { clk displow[3] } "NODE_NAME" } "" } } { "ctrl.vhd" "" { Text "D:/dingshi/ctrl.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns 83.33 % " "Info: Total cell delay = 2.000 ns ( 83.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns 16.67 % " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" {  } {  } 0}  } { { "D:/dingshi/db/ctrl_cmp.qrpt" "" { Report "D:/dingshi/db/ctrl_cmp.qrpt" Compiler "ctrl" "UNKNOWN" "V1" "D:/dingshi/db/ctrl.quartus_db" { Floorplan "D:/dingshi/" "" "2.400 ns" { clk displow[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.400 ns" { clk clk~out displow[3] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "1.300 ns + " "Info: + Micro hold delay of destination is 1.300 ns" {  } { { "ctrl.vhd" "" { Text "D:/dingshi/ctrl.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.700 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns cn 1 PIN PIN_124 11 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_124; Fanout = 11; PIN Node = 'cn'" {  } { { "D:/dingshi/db/ctrl_cmp.qrpt" "" { Report "D:/dingshi/db/ctrl_cmp.qrpt" Compiler "ctrl" "UNKNOWN" "V1" "D:/dingshi/db/ctrl.quartus_db" { Floorplan "D:/dingshi/" "" "" { cn } "NODE_NAME" } "" } } { "ctrl.vhd" "" { Text "D:/dingshi/ctrl.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.400 ns) 3.600 ns rtl~764 2 COMB LC2_B36 2 " "Info: 2: + IC(0.200 ns) + CELL(1.400 ns) = 3.600 ns; Loc. = LC2_B36; Fanout = 2; COMB Node = 'rtl~764'" {  } { { "D:/dingshi/db/ctrl_cmp.qrpt" "" { Report "D:/dingshi/db/ctrl_cmp.qrpt" Compiler "ctrl" "UNKNOWN" "V1" "D:/dingshi/db/ctrl.quartus_db" { Floorplan "D:/dingshi/" "" "1.600 ns" { cn rtl~764 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(0.800 ns) 4.700 ns displow\[3\] 3 REG LC6_B36 8 " "Info: 3: + IC(0.300 ns) + CELL(0.800 ns) = 4.700 ns; Loc. = LC6_B36; Fanout = 8; REG Node = 'displow\[3\]'" {  } { { "D:/dingshi/db/ctrl_cmp.qrpt" "" { Report "D:/dingshi/db/ctrl_cmp.qrpt" Compiler "ctrl" "UNKNOWN" "V1" "D:/dingshi/db/ctrl.quartus_db" { Floorplan "D:/dingshi/" "" "1.100 ns" { rtl~764 displow[3] } "NODE_NAME" } "" } } { "ctrl.vhd" "" { Text "D:/dingshi/ctrl.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.200 ns 89.36 % " "Info: Total cell delay = 4.200 ns ( 89.36 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.500 ns 10.64 % " "Info: Total interconnect delay = 0.500 ns ( 10.64 % )" {  } {  } 0}  } { { "D:/dingshi/db/ctrl_cmp.qrpt" "" { Report "D:/dingshi/db/ctrl_cmp.qrpt" Compiler "ctrl" "UNKNOWN" "V1" "D:/dingshi/db/ctrl.quartus_db" { Floorplan "D:/dingshi/" "" "4.700 ns" { cn rtl~764 displow[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "4.700 ns" { cn cn~out rtl~764 displow[3] } { 0.000ns 0.000ns 0.200ns 0.300ns } { 0.000ns 2.000ns 1.400ns 0.800ns } } }  } 0}  } { { "D:/dingshi/db/ctrl_cmp.qrpt" "" { Report "D:/dingshi/db/ctrl_cmp.qrpt" Compiler "ctrl" "UNKNOWN" "V1" "D:/dingshi/db/ctrl.quartus_db" { Floorplan "D:/dingshi/" "" "2.400 ns" { clk displow[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.400 ns" { clk clk~out displow[3] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } } { "D:/dingshi/db/ctrl_cmp.qrpt" "" { Report "D:/dingshi/db/ctrl_cmp.qrpt" Compiler "ctrl" "UNKNOWN" "V1" "D:/dingshi/db/ctrl.quartus_db" { Floorplan "D:/dingshi/" "" "4.700 ns" { cn rtl~764 displow[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "4.700 ns" { cn cn~out rtl~764 displow[3] } { 0.000ns 0.000ns 0.200ns 0.300ns } { 0.000ns 2.000ns 1.400ns 0.800ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Dec 24 23:09:16 2008 " "Info: Processing ended: Wed Dec 24 23:09:16 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}