ctrl.map.rpt

quarters2编写的定时器.vhd为源程序

;     -- Total 3-input functions    ; 8       ;
;     -- Total 2-input functions    ; 10      ;
;     -- Total 1-input functions    ; 6       ;
;     -- Total 0-input functions    ; 0       ;
; Combinational cells for routing   ; 0       ;
; Total registers                   ; 14      ;
; Total logic cells in carry chains ; 10      ;
; I/O pins                          ; 12      ;
; Maximum fan-out node              ; clk     ;
; Maximum fan-out                   ; 14      ;
; Total fan-out                     ; 159     ;
; Average fan-out                   ; 3.18    ;
+-----------------------------------+---------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                 ;
+----------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------------------------------------------------------------+
; Compilation Hierarchy Node             ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name                                              ;
+----------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------------------------------------------------------------+
; |ctrl                                  ; 38 (25)     ; 14           ; 0           ; 12   ; 24 (21)      ; 1 (1)             ; 13 (3)           ; 10 (0)          ; |ctrl                                                            ;
;    |lpm_counter:\a:cnt[0]_rtl_1|       ; 6 (0)       ; 6            ; 0           ; 0    ; 0 (0)        ; 0 (0)             ; 6 (0)            ; 6 (0)           ; |ctrl|lpm_counter:\a:cnt[0]_rtl_1                                ;
;       |alt_counter_f10ke:wysi_counter| ; 6 (6)       ; 6            ; 0           ; 0    ; 0 (0)        ; 0 (0)             ; 6 (6)            ; 6 (6)           ; |ctrl|lpm_counter:\a:cnt[0]_rtl_1|alt_counter_f10ke:wysi_counter ;
;    |lpm_counter:disphigh_rtl_0|        ; 7 (0)       ; 4            ; 0           ; 0    ; 3 (0)        ; 0 (0)             ; 4 (0)            ; 4 (0)           ; |ctrl|lpm_counter:disphigh_rtl_0                                 ;
;       |alt_counter_f10ke:wysi_counter| ; 7 (7)       ; 4            ; 0           ; 0    ; 3 (3)        ; 0 (0)             ; 4 (4)            ; 4 (4)           ; |ctrl|lpm_counter:disphigh_rtl_0|alt_counter_f10ke:wysi_counter  ;
+----------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------------------------------------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 14    ;
; Number of registers using Synchronous Clear  ; 6     ;
; Number of registers using Synchronous Load   ; 4     ;
; Number of registers using Asynchronous Clear ; 14    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 10    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-----------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: lpm_counter:disphigh_rtl_0 ;
+------------------------+---------+------------------------------------------+
; Parameter Name         ; Value   ; Type                                     ;
+------------------------+---------+------------------------------------------+
; AUTO_CARRY_CHAINS      ; ON      ; AUTO_CARRY                               ;
; IGNORE_CARRY_BUFFERS   ; OFF     ; IGNORE_CARRY                             ;
; AUTO_CASCADE_CHAINS    ; ON      ; AUTO_CASCADE                             ;
; IGNORE_CASCADE_BUFFERS ; OFF     ; IGNORE_CASCADE                           ;
; LPM_WIDTH              ; 4       ; Untyped                                  ;
; LPM_DIRECTION          ; UP      ; Untyped                                  ;
; LPM_MODULUS            ; 0       ; Untyped                                  ;
; LPM_AVALUE             ; UNUSED  ; Untyped                                  ;
; LPM_SVALUE             ; UNUSED  ; Untyped                                  ;
; DEVICE_FAMILY          ; ACEX1K  ; Untyped                                  ;
; CARRY_CHAIN            ; MANUAL  ; Untyped                                  ;
; CARRY_CHAIN_LENGTH     ; 48      ; CARRY_CHAIN_LENGTH                       ;
; NOT_GATE_PUSH_BACK     ; ON      ; NOT_GATE_PUSH_BACK                       ;
; CARRY_CNT_EN           ; SMART   ; Untyped                                  ;
; LABWIDE_SCLR           ; ON      ; Untyped                                  ;
; USE_NEW_VERSION        ; TRUE    ; Untyped                                  ;
; CBXI_PARAMETER         ; NOTHING ; Untyped                                  ;
+------------------------+---------+------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: lpm_counter:\a:cnt[0]_rtl_1 ;
+------------------------+---------+-------------------------------------------+
; Parameter Name         ; Value   ; Type                                      ;
+------------------------+---------+-------------------------------------------+
; AUTO_CARRY_CHAINS      ; ON      ; AUTO_CARRY                                ;
; IGNORE_CARRY_BUFFERS   ; OFF     ; IGNORE_CARRY                              ;
; AUTO_CASCADE_CHAINS    ; ON      ; AUTO_CASCADE                              ;
; IGNORE_CASCADE_BUFFERS ; OFF     ; IGNORE_CASCADE                            ;
; LPM_WIDTH              ; 6       ; Untyped                                   ;
; LPM_DIRECTION          ; UP      ; Untyped                                   ;
; LPM_MODULUS            ; 0       ; Untyped                                   ;
; LPM_AVALUE             ; UNUSED  ; Untyped                                   ;
; LPM_SVALUE             ; UNUSED  ; Untyped                                   ;
; DEVICE_FAMILY          ; ACEX1K  ; Untyped                                   ;
; CARRY_CHAIN            ; MANUAL  ; Untyped                                   ;
; CARRY_CHAIN_LENGTH     ; 48      ; CARRY_CHAIN_LENGTH                        ;
; NOT_GATE_PUSH_BACK     ; ON      ; NOT_GATE_PUSH_BACK                        ;
; CARRY_CNT_EN           ; SMART   ; Untyped                                   ;
; LABWIDE_SCLR           ; ON      ; Untyped                                   ;
; USE_NEW_VERSION        ; TRUE    ; Untyped                                   ;
; CBXI_PARAMETER         ; NOTHING ; Untyped                                   ;
+------------------------+---------+-------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in D:/dingshi/ctrl.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Wed Dec 24 23:08:58 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ctrl -c ctrl
Info: Found 2 design units, including 1 entities, in source file ctrl.vhd
    Info: Found design unit 1: ctrl-rtl
    Info: Found entity 1: ctrl
Info: Elaborating entity "ctrl" for the top level hierarchy
Warning: No clock transition on register "cout~reg0" due to stuck clock or clock enable
Warning: Reduced register "cout~reg0" with stuck clock_enable port to stuck value GND
Info: Inferred 2 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "disphigh[0]~36"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=6) from the following logic: "\a:cnt[0]~0"
Info: Found 1 design units, including 1 entities, in source file ../altera/quartus50/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Info: Found 1 design units, including 1 entities, in source file ../altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf
    Info: Found entity 1: alt_counter_f10ke
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "cout" stuck at GND
Info: Implemented 50 device resources after synthesis - the final resource count might be different
    Info: Implemented 3 input pins
    Info: Implemented 9 output pins
    Info: Implemented 38 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 4 warnings
    Info: Processing ended: Wed Dec 24 23:09:02 2008
    Info: Elapsed time: 00:00:04