ctrl.tan.rpt

quarters2编写的定时器.vhd为源程序

    Info: Processing started: Wed Dec 24 23:09:16 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off ctrl -c ctrl
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 103.09 MHz between source register "lpm_counter:\a:cnt[0]_rtl_1|alt_counter_f10ke:wysi_counter|q[0]" and destination register "displow[1]" (period= 9.7 ns)
    Info: + Longest register to register delay is 8.600 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3_B34; Fanout = 3; REG Node = 'lpm_counter:\a:cnt[0]_rtl_1|alt_counter_f10ke:wysi_counter|q[0]'
        Info: 2: + IC(0.300 ns) + CELL(1.600 ns) = 1.900 ns; Loc. = LC1_B34; Fanout = 1; COMB Node = 'LessThan~168'
        Info: 3: + IC(0.900 ns) + CELL(1.400 ns) = 4.200 ns; Loc. = LC1_B35; Fanout = 3; COMB Node = 'LessThan~169'
        Info: 4: + IC(0.900 ns) + CELL(1.600 ns) = 6.700 ns; Loc. = LC1_B36; Fanout = 4; COMB Node = 'rtl~2'
        Info: 5: + IC(0.900 ns) + CELL(1.000 ns) = 8.600 ns; Loc. = LC3_B35; Fanout = 10; REG Node = 'displow[1]'
        Info: Total cell delay = 5.600 ns ( 65.12 % )
        Info: Total interconnect delay = 3.000 ns ( 34.88 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 2.400 ns
            Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 20; CLK Node = 'clk'
            Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC3_B35; Fanout = 10; REG Node = 'displow[1]'
            Info: Total cell delay = 2.000 ns ( 83.33 % )
            Info: Total interconnect delay = 0.400 ns ( 16.67 % )
        Info: - Longest clock path from clock "clk" to source register is 2.400 ns
            Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 20; CLK Node = 'clk'
            Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC3_B34; Fanout = 3; REG Node = 'lpm_counter:\a:cnt[0]_rtl_1|alt_counter_f10ke:wysi_counter|q[0]'
            Info: Total cell delay = 2.000 ns ( 83.33 % )
            Info: Total interconnect delay = 0.400 ns ( 16.67 % )
    Info: + Micro clock to output delay of source is 0.500 ns
    Info: + Micro setup delay of destination is 0.600 ns
Info: tsu for register "displow[0]" (data pin = "cn", clock pin = "clk") is 5.600 ns
    Info: + Longest pin to register delay is 7.400 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_124; Fanout = 11; PIN Node = 'cn'
        Info: 2: + IC(0.300 ns) + CELL(1.400 ns) = 3.700 ns; Loc. = LC1_B33; Fanout = 9; COMB Node = 'lpm_counter:disphigh_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]~177'
        Info: 3: + IC(1.000 ns) + CELL(1.600 ns) = 6.300 ns; Loc. = LC5_B35; Fanout = 1; COMB Node = 'rtl~761'
        Info: 4: + IC(0.300 ns) + CELL(0.800 ns) = 7.400 ns; Loc. = LC7_B35; Fanout = 9; REG Node = 'displow[0]'
        Info: Total cell delay = 5.800 ns ( 78.38 % )
        Info: Total interconnect delay = 1.600 ns ( 21.62 % )
    Info: + Micro setup delay of destination is 0.600 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.400 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 20; CLK Node = 'clk'
        Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC7_B35; Fanout = 9; REG Node = 'displow[0]'
        Info: Total cell delay = 2.000 ns ( 83.33 % )
        Info: Total interconnect delay = 0.400 ns ( 16.67 % )
Info: tco from clock "clk" to destination pin "low[1]" through register "displow[1]" is 11.500 ns
    Info: + Longest clock path from clock "clk" to source register is 2.400 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 20; CLK Node = 'clk'
        Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC3_B35; Fanout = 10; REG Node = 'displow[1]'
        Info: Total cell delay = 2.000 ns ( 83.33 % )
        Info: Total interconnect delay = 0.400 ns ( 16.67 % )
    Info: + Micro clock to output delay of source is 0.500 ns
    Info: + Longest register to pin delay is 8.600 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3_B35; Fanout = 10; REG Node = 'displow[1]'
        Info: 2: + IC(2.300 ns) + CELL(6.300 ns) = 8.600 ns; Loc. = PIN_99; Fanout = 0; PIN Node = 'low[1]'
        Info: Total cell delay = 6.300 ns ( 73.26 % )
        Info: Total interconnect delay = 2.300 ns ( 26.74 % )
Info: th for register "displow[3]" (data pin = "cn", clock pin = "clk") is -1.000 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.400 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 20; CLK Node = 'clk'
        Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC6_B36; Fanout = 8; REG Node = 'displow[3]'
        Info: Total cell delay = 2.000 ns ( 83.33 % )
        Info: Total interconnect delay = 0.400 ns ( 16.67 % )
    Info: + Micro hold delay of destination is 1.300 ns
    Info: - Shortest pin to register delay is 4.700 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_124; Fanout = 11; PIN Node = 'cn'
        Info: 2: + IC(0.200 ns) + CELL(1.400 ns) = 3.600 ns; Loc. = LC2_B36; Fanout = 2; COMB Node = 'rtl~764'
        Info: 3: + IC(0.300 ns) + CELL(0.800 ns) = 4.700 ns; Loc. = LC6_B36; Fanout = 8; REG Node = 'displow[3]'
        Info: Total cell delay = 4.200 ns ( 89.36 % )
        Info: Total interconnect delay = 0.500 ns ( 10.64 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Wed Dec 24 23:09:16 2008
    Info: Elapsed time: 00:00:01