fir3.vhd

3阶FIR

package eight_bit_int is --user defined types
subtype byte is integer range -2048 to 2047;
type array_byte is array(0 to 2)of byte;
end eight_bit_int;
library work;
use work.eight_bit_int.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity fir3 is   ----->interface
port (clk : in  std_logic;
  x : in  byte;
  y: out byte);
end fir3;
architecture flex of fir3 is
signal tap :array_byte; --tapped delay line of bytes
begin 
p1:process   ----->behavioral style
begin 
wait until clk='1';
--the coefficients are [0.625 1.25 0.125].
y<=tap(2)/2+tap(2)/8
   +tap(1)+tap(1)/4
   +tap(0)/8;
for i in 2 downto 1 loop
tap(i)<=tap(i-1);--tapped delay line:shift one
end loop;
tap(0)<=x;
end process;
end flex;