forcedeth.c

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#define PHY_REALTEK_INIT1	0x0000
#define PHY_REALTEK_INIT2	0x8e00
#define PHY_REALTEK_INIT3 	0x0001
#define PHY_REALTEK_INIT4	0xad17

#define PHY_GIGABIT	0x0100

#define PHY_TIMEOUT	0x1
#define PHY_ERROR	0x2

#define PHY_100	0x1
#define PHY_1000	0x2
#define PHY_HALF	0x100

#define NV_PAUSEFRAME_RX_CAPABLE 0x0001
#define NV_PAUSEFRAME_TX_CAPABLE 0x0002
#define NV_PAUSEFRAME_RX_ENABLE  0x0004
#define NV_PAUSEFRAME_TX_ENABLE  0x0008
#define NV_PAUSEFRAME_RX_REQ     0x0010
#define NV_PAUSEFRAME_TX_REQ     0x0020
#define NV_PAUSEFRAME_AUTONEG    0x0040

/* MSI/MSI-X defines */
#define NV_MSI_X_MAX_VECTORS  8
#define NV_MSI_X_VECTORS_MASK 0x000f
#define NV_MSI_CAPABLE        0x0010
#define NV_MSI_X_CAPABLE      0x0020
#define NV_MSI_ENABLED        0x0040
#define NV_MSI_X_ENABLED      0x0080

#define NV_MSI_X_VECTOR_ALL   0x0
#define NV_MSI_X_VECTOR_RX    0x0
#define NV_MSI_X_VECTOR_TX    0x1
#define NV_MSI_X_VECTOR_OTHER 0x2

#define NV_RESTART_TX	      0x1
#define NV_RESTART_RX	      0x2
#define NVLAN_DISABLE_ALL_FEATURES  do { \
	msi = NV_MSI_INT_DISABLED; \
	msix = NV_MSIX_INT_DISABLED; \
	scatter_gather = NV_SCATTER_GATHER_DISABLED; \
	tso_offload = NV_TSO_DISABLED; \
	tx_checksum_offload = NV_TX_CHECKSUM_DISABLED; \
	rx_checksum_offload = NV_RX_CHECKSUM_DISABLED; \
	tx_flow_control = NV_TX_FLOW_CONTROL_DISABLED; \
	rx_flow_control = NV_RX_FLOW_CONTROL_DISABLED; \
	wol = NV_WOL_DISABLED; \
	tagging_8021pq = NV_8021PQ_DISABLED; \
} while (0)

struct nv_ethtool_str {
	char name[ETH_GSTRING_LEN];
};

static const struct nv_ethtool_str nv_estats_str[] = {
	{ "tx_dropped" },
	{ "tx_fifo_errors" },
	{ "tx_carrier_errors" },
	{ "tx_packets" },
	{ "tx_bytes" },
	{ "rx_crc_errors" },
	{ "rx_over_errors" },
	{ "rx_errors_total" },
	{ "rx_packets" },
	{ "rx_bytes" },

	/* hardware counters */
	{ "tx_zero_rexmt" },
	{ "tx_one_rexmt" },
	{ "tx_many_rexmt" },
	{ "tx_late_collision" },
	{ "tx_excess_deferral" },
	{ "tx_retry_error" },
	{ "rx_frame_error" },
	{ "rx_extra_byte" },
	{ "rx_late_collision" },
	{ "rx_runt" },
	{ "rx_frame_too_long" },
	{ "rx_frame_align_error" },
	{ "rx_length_error" },
	{ "rx_unicast" },
	{ "rx_multicast" },
	{ "rx_broadcast" },
	{ "tx_deferral" },
	{ "tx_pause" },
	{ "rx_pause" },
	{ "rx_drop_frame" }
};

struct nv_ethtool_stats {
	u64 tx_dropped;
	u64 tx_fifo_errors;
	u64 tx_carrier_errors;
	u64 tx_packets;
	u64 tx_bytes;
	u64 rx_crc_errors;
	u64 rx_over_errors;
	u64 rx_errors_total;
	u64 rx_packets;
	u64 rx_bytes;

	/* hardware counters */
	u64 tx_zero_rexmt;
	u64 tx_one_rexmt;
	u64 tx_many_rexmt;
	u64 tx_late_collision;
	u64 tx_excess_deferral;
	u64 tx_retry_error;
	u64 rx_frame_error;
	u64 rx_extra_byte;
	u64 rx_late_collision;
	u64 rx_runt;
	u64 rx_frame_too_long;
	u64 rx_frame_align_error;
	u64 rx_length_error;
	u64 rx_unicast;
	u64 rx_multicast;
	u64 rx_broadcast;
	u64 tx_deferral;
	u64 tx_pause;
	u64 rx_pause;
	u64 rx_drop_frame;
};
#define NV_DEV_STATISTICS_V2_COUNT (sizeof(struct nv_ethtool_stats)/sizeof(u64))
#define NV_DEV_STATISTICS_V1_COUNT (NV_DEV_STATISTICS_V2_COUNT - 4)
#define NV_DEV_STATISTICS_SW_COUNT 10

/* diagnostics */
#define NV_TEST_COUNT_BASE 3
#define NV_TEST_COUNT_EXTENDED 4

static const struct nv_ethtool_str nv_etests_str[] = {
	{ "link      (online/offline)" },
	{ "register  (offline)       " },
	{ "interrupt (offline)       " },
	{ "loopback  (offline)       " }
};

struct register_test {
	u32 reg;
	u32 mask;
};

static const struct register_test nv_registers_test[] = {
	{ NvRegUnknownSetupReg6, 0x01 },
	{ NvRegMisc1, 0x03c },
	{ NvRegOffloadConfig, 0x03ff },
	{ NvRegMulticastAddrA, 0xffffffff },
	{ NvRegTxWatermark, 0x0ff },
	{ NvRegWakeUpFlags, 0x07777 },
	{ 0,0 }
};

struct nv_skb_map {
	struct sk_buff *skb;
	dma_addr_t dma;
	unsigned int dma_len;
};

/*
 * SMP locking:
 * All hardware access under dev->priv->lock, except the performance
 * critical parts:
 * - rx is (pseudo-) lockless: it relies on the single-threading provided
 *	by the arch code for interrupts.
 * - tx setup is lockless: it relies on dev->xmit_lock. Actual submission
 *	needs dev->priv->lock :-(
 * - set_multicast_list: preparation lockless, relies on dev->xmit_lock.
 */

/* in dev: base, irq */
struct fe_priv {

	/* fields used in fast path are grouped together 
	   for better cache performance
	 */
	spinlock_t lock;
	spinlock_t timer_lock;
	void __iomem *base;
	struct pci_dev *pci_dev;
	u32 txrxctl_bits;
	int stop_tx;
	int need_linktimer;
	unsigned long link_timeout;
	u32 irqmask;
	u32 msi_flags;

	unsigned int rx_buf_sz;
	struct vlan_group *vlangrp;
	int tx_ring_size;
	int rx_csum;

	/*
	 * rx specific fields in fast path
	 */
	ring_type get_rx __attribute__((aligned(L1_CACHE_BYTES)));
	ring_type put_rx, first_rx, last_rx;
	struct nv_skb_map *get_rx_ctx, *put_rx_ctx;
	struct nv_skb_map *first_rx_ctx, *last_rx_ctx;

	/*
	 * tx specific fields in fast path
	 */
	ring_type get_tx __attribute__((aligned(L1_CACHE_BYTES)));
	ring_type put_tx, first_tx, last_tx;
	struct nv_skb_map *get_tx_ctx, *put_tx_ctx;
	struct nv_skb_map *first_tx_ctx, *last_tx_ctx;

	struct nv_skb_map *rx_skb;
	struct nv_skb_map *tx_skb;

	/* General data:
	 * Locking: spin_lock(&np->lock); */
	struct net_device_stats stats;
	struct nv_ethtool_stats estats;
	int in_shutdown;
	u32 linkspeed;
	int duplex;
	int speed_duplex;
	int autoneg;
	int fixed_mode;
	int phyaddr;
	int wolenabled;
	unsigned int phy_oui;
	unsigned int phy_model;
	u16 gigabit;
	int intr_test;
	int recover_error;

	/* General data: RO fields */
	dma_addr_t ring_addr;
	u32 orig_mac[2];
	u32 desc_ver;
	u32 vlanctl_bits;
	u32 driver_data;
	u32 register_size;
	u32 mac_in_use;

	/* rx specific fields.
	 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
	 */
	ring_type rx_ring;
	unsigned int pkt_limit;
	struct timer_list oom_kick;
	struct timer_list nic_poll;
	struct timer_list stats_poll;
	u32 nic_poll_irq;
	int rx_ring_size;
	u32 rx_len_errors;
	/*
	 * tx specific fields.
	 */
	ring_type tx_ring;
	u32 tx_flags;
	int tx_limit_start;
	int tx_limit_stop;


	/* msi/msi-x fields */
	struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS];

	/* flow control */
	u32 pause_flags;
	u32 led_stats[3];
	u32 saved_config_space[64];
	u32 saved_nvregphyinterface;
#if NVVER < SUSE10
	u32 pci_state[16];
#endif
	/* msix table */
	struct nvmsi_msg nvmsg[NV_MSI_X_MAX_VECTORS];
	unsigned long msix_pa_addr;
};

/*
 * Maximum number of loops until we assume that a bit in the irq mask
 * is stuck. Overridable with module param.
 */
static int max_interrupt_work = 5;

/*
 * Optimization can be either throuput mode or cpu mode
 * 
 * Throughput Mode: Every tx and rx packet will generate an interrupt.
 * CPU Mode: Interrupts are controlled by a timer.
 */
enum {
	NV_OPTIMIZATION_MODE_THROUGHPUT, 
	NV_OPTIMIZATION_MODE_CPU
};
static int optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT;

/*
 * Poll interval for timer irq
 *
 * This interval determines how frequent an interrupt is generated.
 * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
 * Min = 0, and Max = 65535
 */
static int poll_interval = -1;

/*
 * MSI interrupts
 */
enum {
	NV_MSI_INT_DISABLED,
	NV_MSI_INT_ENABLED
};

#ifdef CONFIG_PCI_MSI 
static int msi = NV_MSI_INT_ENABLED;
#else
static int msi = NV_MSI_INT_DISABLED;
#endif

/*
 * MSIX interrupts
 */
enum {
	NV_MSIX_INT_DISABLED, 
	NV_MSIX_INT_ENABLED
};

#ifdef CONFIG_PCI_MSI 
static int msix = NV_MSIX_INT_ENABLED;
#else
static int msix = NV_MSIX_INT_DISABLED;
#endif
/*
 * PHY Speed and Duplex
 */
enum {
	NV_SPEED_DUPLEX_AUTO,
	NV_SPEED_DUPLEX_10_HALF_DUPLEX,
	NV_SPEED_DUPLEX_10_FULL_DUPLEX,
	NV_SPEED_DUPLEX_100_HALF_DUPLEX,
	NV_SPEED_DUPLEX_100_FULL_DUPLEX,
	NV_SPEED_DUPLEX_1000_FULL_DUPLEX
};
static int speed_duplex = NV_SPEED_DUPLEX_AUTO;

/*
 * PHY autonegotiation
 */
static int autoneg = AUTONEG_ENABLE;

/*
 * Scatter gather
 */
enum {
	NV_SCATTER_GATHER_DISABLED,
	NV_SCATTER_GATHER_ENABLED
};
static int scatter_gather = NV_SCATTER_GATHER_ENABLED;

/*
 * TCP Segmentation Offload (TSO)
 */
enum {
	NV_TSO_DISABLED,
	NV_TSO_ENABLED
};
static int tso_offload = NV_TSO_ENABLED;

/*
 * MTU settings
 */
static int mtu = ETH_DATA_LEN;

/*
 * Tx checksum offload
 */
enum {
	NV_TX_CHECKSUM_DISABLED, 
	NV_TX_CHECKSUM_ENABLED 
};
static int tx_checksum_offload = NV_TX_CHECKSUM_ENABLED;

/*
 * Rx checksum offload
 */
enum {
	NV_RX_CHECKSUM_DISABLED, 
	NV_RX_CHECKSUM_ENABLED 
};
static int rx_checksum_offload = NV_RX_CHECKSUM_ENABLED;

/*
 * Tx ring size
 */
static int tx_ring_size = TX_RING_DEFAULT;

/*
 * Rx ring size
 */
static int rx_ring_size = RX_RING_DEFAULT;

/*
 * Tx flow control
 */
enum {
	NV_TX_FLOW_CONTROL_DISABLED, 
	NV_TX_FLOW_CONTROL_ENABLED
};
static int tx_flow_control = NV_TX_FLOW_CONTROL_ENABLED;

/*
 * Rx flow control
 */
enum {
	NV_RX_FLOW_CONTROL_DISABLED, 
	NV_RX_FLOW_CONTROL_ENABLED
};
static int rx_flow_control = NV_RX_FLOW_CONTROL_ENABLED;

/*
 * DMA 64bit
 */
enum {
	NV_DMA_64BIT_DISABLED,
	NV_DMA_64BIT_ENABLED
};
static int dma_64bit = NV_DMA_64BIT_ENABLED;

/*
 * Wake On Lan
 */
enum {
	NV_WOL_DISABLED,
	NV_WOL_ENABLED
};
static int wol = NV_WOL_DISABLED;

/*
 * Tagging 802.1pq
 */
enum {
	NV_8021PQ_DISABLED,
	NV_8021PQ_ENABLED
};
static int tagging_8021pq = NV_8021PQ_ENABLED;

enum {
	NV_LOW_POWER_DISABLED,
	NV_LOW_POWER_ENABLED
};
static int lowpowerspeed = NV_LOW_POWER_ENABLED;

static int debug = 0;

#if NVVER < RHES4
static inline unsigned long nv_msecs_to_jiffies(const unsigned int m)
{