forcedeth.c

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/*
 * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
 *
 * Note: This driver is a cleanroom reimplementation based on reverse
 *      engineered documentation written by Carl-Daniel Hailfinger
 *      and Andrew de Quincey. It's neither supported nor endorsed
 *      by NVIDIA Corp. Use at your own risk.
 *
 * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
 * trademarks of NVIDIA Corporation in the United States and other
 * countries.
 *
 * Copyright (C) 2003,4,5 Manfred Spraul
 * Copyright (C) 2004 Andrew de Quincey (wol support)
 * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
 *		IRQ rate fixes, bigendian fixes, cleanups, verification)
 * Copyright (c) 2004 NVIDIA Corporation
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 *
 * Changelog:
 * 	0.01: 05 Oct 2003: First release that compiles without warnings.
 * 	0.02: 05 Oct 2003: Fix bug for nv_drain_tx: do not try to free NULL skbs.
 * 			   Check all PCI BARs for the register window.
 * 			   udelay added to mii_rw.
 * 	0.03: 06 Oct 2003: Initialize dev->irq.
 * 	0.04: 07 Oct 2003: Initialize np->lock, reduce handled irqs, add printks.
 * 	0.05: 09 Oct 2003: printk removed again, irq status print tx_timeout.
 * 	0.06: 10 Oct 2003: MAC Address read updated, pff flag generation updated,
 * 			   irq mask updated
 * 	0.07: 14 Oct 2003: Further irq mask updates.
 * 	0.08: 20 Oct 2003: rx_desc.Length initialization added, nv_alloc_rx refill
 * 			   added into irq handler, NULL check for drain_ring.
 * 	0.09: 20 Oct 2003: Basic link speed irq implementation. Only handle the
 * 			   requested interrupt sources.
 * 	0.10: 20 Oct 2003: First cleanup for release.
 * 	0.11: 21 Oct 2003: hexdump for tx added, rx buffer sizes increased.
 * 			   MAC Address init fix, set_multicast cleanup.
 * 	0.12: 23 Oct 2003: Cleanups for release.
 * 	0.13: 25 Oct 2003: Limit for concurrent tx packets increased to 10.
 * 			   Set link speed correctly. start rx before starting
 * 			   tx (nv_start_rx sets the link speed).
 * 	0.14: 25 Oct 2003: Nic dependant irq mask.
 * 	0.15: 08 Nov 2003: fix smp deadlock with set_multicast_list during
 * 			   open.
 * 	0.16: 15 Nov 2003: include file cleanup for ppc64, rx buffer size
 * 			   increased to 1628 bytes.
 * 	0.17: 16 Nov 2003: undo rx buffer size increase. Substract 1 from
 * 			   the tx length.
 * 	0.18: 17 Nov 2003: fix oops due to late initialization of dev_stats
 * 	0.19: 29 Nov 2003: Handle RxNoBuf, detect & handle invalid mac
 * 			   addresses, really stop rx if already running
 * 			   in nv_start_rx, clean up a bit.
 * 	0.20: 07 Dec 2003: alloc fixes
 * 	0.21: 12 Jan 2004: additional alloc fix, nic polling fix.
 *	0.22: 19 Jan 2004: reprogram timer to a sane rate, avoid lockup
 *			   on close.
 *	0.23: 26 Jan 2004: various small cleanups
 *	0.24: 27 Feb 2004: make driver even less anonymous in backtraces
 *	0.25: 09 Mar 2004: wol support
 *	0.26: 03 Jun 2004: netdriver specific annotation, sparse-related fixes
 *	0.27: 19 Jun 2004: Gigabit support, new descriptor rings,
 *			   added CK804/MCP04 device IDs, code fixes
 *			   for registers, link status and other minor fixes.
 *	0.28: 21 Jun 2004: Big cleanup, making driver mostly endian safe
 *	0.29: 31 Aug 2004: Add backup timer for link change notification.
 *	0.30: 25 Sep 2004: rx checksum support for nf 250 Gb. Add rx reset
 *			   into nv_close, otherwise reenabling for wol can
 *			   cause DMA to kfree'd memory.
 *	0.31: 14 Nov 2004: ethtool support for getting/setting link
 *			   capabilities.
 *	0.32: 16 Apr 2005: RX_ERROR4 handling added.
 *	0.33: 16 May 2005: Support for MCP51 added.
 *	0.34: 18 Jun 2005: Add DEV_NEED_LINKTIMER to all nForce nics.
 *	0.35: 26 Jun 2005: Support for MCP55 added.
 *	0.36: 28 Jun 2005: Add jumbo frame support.
 *	0.37: 10 Jul 2005: Additional ethtool support, cleanup of pci id list
 *	0.38: 16 Jul 2005: tx irq rewrite: Use global flags instead of
 *			   per-packet flags.
 *	0.39: 18 Jul 2005: Add 64bit descriptor support.
 *	0.40: 19 Jul 2005: Add support for mac address change.
 *	0.41: 30 Jul 2005: Write back original MAC in nv_close instead
 *			   of nv_remove
 *	0.42: 06 Aug 2005: Fix lack of link speed initialization
 *			   in the second (and later) nv_open call
 *	0.43: 10 Aug 2005: Add support for tx checksum.
 *	0.44: 20 Aug 2005: Add support for scatter gather and segmentation.
 *	0.45: 18 Sep 2005: Remove nv_stop/start_rx from every link check
 *	0.46: 20 Oct 2005: Add irq optimization modes.
 *	0.47: 26 Oct 2005: Add phyaddr 0 in phy scan.
 *	0.48: 24 Dec 2005: Disable TSO, bugfix for pci_map_single
 *	0.49: 10 Dec 2005: Fix tso for large buffers.
 *	0.50: 20 Jan 2006: Add 8021pq tagging support.
 *	0.51: 20 Jan 2006: Add 64bit consistent memory allocation for rings.
 *	0.52: 20 Jan 2006: Add MSI/MSIX support.
 *	0.53: 19 Mar 2006: Fix init from low power mode and add hw reset.
 *	0.54: 21 Mar 2006: Fix spin locks for multi irqs and cleanup.
 *	0.55: 22 Mar 2006: Add flow control (pause frame).
 *	0.56: 22 Mar 2006: Additional ethtool and moduleparam support.
 *	0.57: 14 May 2006: Moved mac address writes to nv_probe and nv_remove.
 *	0.58: 20 May 2006: Optimized rx and tx data paths.
 *	0.59: 31 May 2006: Added support for sideband management unit.
 *	0.60: 31 May 2006: Added support for recoverable error.
 *	0.61: 18 Jul 2006: Added support for suspend/resume.
 *	0.62: 16 Jan 2007: Fixed statistics, mgmt communication, and low phy speed on S5.
 *
 * Known bugs:
 * We suspect that on some hardware no TX done interrupts are generated.
 * This means recovery from netif_stop_queue only happens if the hw timer
 * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
 * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
 * If your hardware reliably generates tx done interrupts, then you can remove
 * DEV_NEED_TIMERIRQ from the driver_data flags.
 * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
 * superfluous timer interrupts from the nic.
 */
#define FORCEDETH_VERSION		"0.62-Driver Package V1.25"
#define DRV_NAME			"forcedeth"
#define DRV_DATE			"2008/01/30"

#include <linux/module.h>
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/interrupt.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/delay.h>
#include <linux/spinlock.h>
#include <linux/ethtool.h>
#include <linux/timer.h>
#include <linux/skbuff.h>
#include <linux/mii.h>
#include <linux/random.h>
#include <linux/init.h>
#include <linux/if_vlan.h>
#include <linux/rtnetlink.h>
#include <linux/reboot.h>
#include <linux/version.h>

#define RHES3  		0
#define SLES9	 	1
#define RHES4		2
#define SUSE10		3 
#define	FEDORA5		4 
#define	FEDORA6		5
#define	SLES10U1    	5
#define	FEDORA7		6
#define	OPENSUSE10U3	7
#define NVNEW	8

#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,22)
#define NVVER NVNEW  
#elif LINUX_VERSION_CODE > KERNEL_VERSION(2,6,21)
#define NVVER OPENSUSE10U3
#elif LINUX_VERSION_CODE > KERNEL_VERSION(2,6,18)
#define NVVER FEDORA7
#elif LINUX_VERSION_CODE > KERNEL_VERSION(2,6,17)
#define NVVER FEDORA6
#elif LINUX_VERSION_CODE > KERNEL_VERSION(2,6,13)
#define NVVER FEDORA5		
#elif LINUX_VERSION_CODE > KERNEL_VERSION(2,6,9)
#define NVVER SUSE10		
#elif LINUX_VERSION_CODE > KERNEL_VERSION(2,6,6)
#define NVVER RHES4	
#elif LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0)
#define NVVER SLES9	
#else
#define NVVER RHES3  	
#endif

#if NVVER > RHES3
#include <linux/dma-mapping.h>
#else
#include <linux/forcedeth-compat.h>
#endif

#include <asm/irq.h>
#include <asm/io.h>
#include <asm/uaccess.h>
#include <asm/system.h>

#ifdef  NVLAN_DEBUG
#define dprintk			printk
#else
#define dprintk(x...)		do { } while (0)
#endif

#define DPRINTK(nlevel,klevel,args...) (void)((debug & NETIF_MSG_##nlevel) && printk(klevel args))

 /* pci_ids.h */
#ifndef PCI_DEVICE_ID_NVIDIA_NVENET_12
#define PCI_DEVICE_ID_NVIDIA_NVENET_12 0x0268 
#endif

#ifndef PCI_DEVICE_ID_NVIDIA_NVENET_13
#define PCI_DEVICE_ID_NVIDIA_NVENET_13 0x0269 
#endif

#ifndef PCI_DEVICE_ID_NVIDIA_NVENET_14
#define PCI_DEVICE_ID_NVIDIA_NVENET_14 0x0372 
#endif

#ifndef PCI_DEVICE_ID_NVIDIA_NVENET_15
#define PCI_DEVICE_ID_NVIDIA_NVENET_15 0x0373 
#endif

#ifndef PCI_DEVICE_ID_NVIDIA_NVENET_16
#define PCI_DEVICE_ID_NVIDIA_NVENET_16 0x03E5
#endif

#ifndef PCI_DEVICE_ID_NVIDIA_NVENET_17
#define PCI_DEVICE_ID_NVIDIA_NVENET_17 0x03E6 
#endif

#ifndef PCI_DEVICE_ID_NVIDIA_NVENET_18
#define PCI_DEVICE_ID_NVIDIA_NVENET_18 0x03EE 
#endif

#ifndef PCI_DEVICE_ID_NVIDIA_NVENET_19
#define PCI_DEVICE_ID_NVIDIA_NVENET_19 0x03EF 
#endif

#ifndef PCI_DEVICE_ID_NVIDIA_NVENET_20
#define PCI_DEVICE_ID_NVIDIA_NVENET_20 0x0450 
#endif

#ifndef PCI_DEVICE_ID_NVIDIA_NVENET_21
#define PCI_DEVICE_ID_NVIDIA_NVENET_21 0x0451 
#endif

#ifndef PCI_DEVICE_ID_NVIDIA_NVENET_22
#define PCI_DEVICE_ID_NVIDIA_NVENET_22 0x0452 
#endif

#ifndef PCI_DEVICE_ID_NVIDIA_NVENET_23
#define PCI_DEVICE_ID_NVIDIA_NVENET_23 0x0453 
#endif

#ifndef PCI_DEVICE_ID_NVIDIA_NVENET_24
#define PCI_DEVICE_ID_NVIDIA_NVENET_24 0x054c
#endif

#ifndef PCI_DEVICE_ID_NVIDIA_NVENET_25
#define PCI_DEVICE_ID_NVIDIA_NVENET_25 0x054d
#endif

#ifndef PCI_DEVICE_ID_NVIDIA_NVENET_26
#define PCI_DEVICE_ID_NVIDIA_NVENET_26 0x054e
#endif

#ifndef PCI_DEVICE_ID_NVIDIA_NVENET_27
#define PCI_DEVICE_ID_NVIDIA_NVENET_27 0x054f
#endif

 /* mii.h */
#ifndef PCI_DEVICE_ID_NVIDIA_NVENET_28
#define PCI_DEVICE_ID_NVIDIA_NVENET_28 0x07dc
#endif

#ifndef PCI_DEVICE_ID_NVIDIA_NVENET_29
#define PCI_DEVICE_ID_NVIDIA_NVENET_29 0x07dd
#endif

#ifndef PCI_DEVICE_ID_NVIDIA_NVENET_30
#define PCI_DEVICE_ID_NVIDIA_NVENET_30 0x07de
#endif

#ifndef PCI_DEVICE_ID_NVIDIA_NVENET_31
#define PCI_DEVICE_ID_NVIDIA_NVENET_31 0x07df
#endif

#ifndef PCI_DEVICE_ID_NVIDIA_NVENET_32
#define PCI_DEVICE_ID_NVIDIA_NVENET_32 0x0760
#endif

#ifndef PCI_DEVICE_ID_NVIDIA_NVENET_33
#define PCI_DEVICE_ID_NVIDIA_NVENET_33 0x0761
#endif

#ifndef PCI_DEVICE_ID_NVIDIA_NVENET_34
#define PCI_DEVICE_ID_NVIDIA_NVENET_34 0x0762
#endif

#ifndef PCI_DEVICE_ID_NVIDIA_NVENET_35
#define PCI_DEVICE_ID_NVIDIA_NVENET_35 0x0763
#endif

#ifndef PCI_DEVICE_ID_NVIDIA_NVENET_36
#define PCI_DEVICE_ID_NVIDIA_NVENET_36 0x0AB0
#endif

#ifndef PCI_DEVICE_ID_NVIDIA_NVENET_37
#define PCI_DEVICE_ID_NVIDIA_NVENET_37 0x0AB1
#endif

#ifndef PCI_DEVICE_ID_NVIDIA_NVENET_38
#define PCI_DEVICE_ID_NVIDIA_NVENET_38 0x0AB2
#endif

#ifndef PCI_DEVICE_ID_NVIDIA_NVENET_39
#define PCI_DEVICE_ID_NVIDIA_NVENET_39 0x0AB3
#endif

#ifndef ADVERTISE_1000HALF
#define ADVERTISE_1000HALF	0x0100
#endif
#ifndef ADVERTISE_1000FULL
#define ADVERTISE_1000FULL	0x0200
#endif
#ifndef ADVERTISE_PAUSE_CAP
#define ADVERTISE_PAUSE_CAP	0x0400
#endif
#ifndef ADVERTISE_PAUSE_ASYM
#define ADVERTISE_PAUSE_ASYM	0x0800
#endif
#ifndef MII_CTRL1000
#define MII_CTRL1000		0x09 
#endif
#ifndef MII_STAT1000
#define MII_STAT1000		0x0A 
#endif
#ifndef LPA_1000FULL
#define LPA_1000FULL		0x0800
#endif
#ifndef LPA_1000HALF
#define LPA_1000HALF		0x0400 
#endif
#ifndef LPA_PAUSE_CAP
#define LPA_PAUSE_CAP		0x0400
#endif
#ifndef LPA_PAUSE_ASYM
#define LPA_PAUSE_ASYM		0x0800
#endif
#ifndef BMCR_SPEED1000
#define BMCR_SPEED1000		0x0040	/* MSB of Speed (1000)         */
#endif

#ifndef NETDEV_TX_OK
#define NETDEV_TX_OK 		0	/* driver took care of packet */
#endif

#ifndef NETDEV_TX_BUSY
#define NETDEV_TX_BUSY 		1    /* driver tx path was busy*/
#endif

#ifndef DMA_39BIT_MASK
#define DMA_39BIT_MASK		0x0000007fffffffffULL    
#endif

#ifndef __iomem
#define __iomem 
#endif

#ifndef __bitwise
#define __bitwise
#endif

#ifndef __force
#define __force
#endif

#ifndef PCI_D0
#define PCI_D0		((int __bitwise __force) 0)
#endif

#ifndef PM_EVENT_SUSPEND 
#define PM_EVENT_SUSPEND 2 
#endif

#ifndef MODULE_VERSION
#define MODULE_VERSION(ver)
#endif

#if NVVER > FEDORA6
#define CHECKSUM_HW CHECKSUM_PARTIAL
#endif

#if NVVER < SUSE10
#define pm_message_t u32
#endif

 /* rx/tx mac addr + type + vlan + align + slack*/
#ifndef RX_NIC_BUFSIZE	
#define RX_NIC_BUFSIZE		(ETH_DATA_LEN + 64)
#endif
 /* even more slack */
#ifndef RX_ALLOC_BUFSIZE	
#define RX_ALLOC_BUFSIZE	(ETH_DATA_LEN + 128)
#endif

#ifndef PCI_DEVICE
#define PCI_DEVICE(vend,dev) \
	 .vendor = (vend), .device = (dev), \
 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
#endif

#if NVVER < RHES4
 struct msix_entry {
	 u16 vector;	/* kernel uses to write allocated vector */
	 u16 entry;	/* driver uses to specify entry, OS writes */
 };
#endif

#ifndef PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET
#define PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET 0x00
#endif

#ifndef PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET 
#define PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET 0x04 
#endif

#ifndef PCI_MSIX_ENTRY_DATA_OFFSET
#define PCI_MSIX_ENTRY_DATA_OFFSET 0x08
#endif 

#ifndef PCI_MSIX_ENTRY_SIZE
#define PCI_MSIX_ENTRY_SIZE 16
#endif

#ifndef PCI_MSIX_FLAGS_BIRMASK
#define PCI_MSIX_FLAGS_BIRMASK		(7 << 0)
#endif

#ifndef PCI_CAP_ID_MSIX
#define PCI_CAP_ID_MSIX 0x11
#endif

#if NVVER > FEDORA7
#define IRQ_FLAG IRQF_SHARED
#else
#define IRQ_FLAG SA_SHIRQ
#endif

/*
 * Hardware access:
 */

#define DEV_NEED_TIMERIRQ	   0x00001  /* set the timer irq flag in the irq mask */
#define DEV_NEED_LINKTIMER	   0x00002  /* poll link settings. Relies on the timer irq */
#define DEV_HAS_LARGEDESC	   0x00004  /* device supports jumbo frames and needs packet format 2 */
#define DEV_HAS_HIGH_DMA           0x00008  /* device supports 64bit dma */