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📄 init.c

📁 MTK的1389KP程序
💻 C
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/***************    MTK CONFIDENTIAL & COPYRIGHTED     ****************/
/***************                                       ****************/
/***************  $Modtime:: 07/04/20 2:33p     $       ****************/
/***************  $Revision:: 21               $       ****************/
/***************                                       ****************/
/*************** Description : Initial, Reset, Hardware****************/
/***************               check routines used for ****************/
/***************               Channel decoder         ****************/
/***************                                       ****************/
/***************     Company : MediaTek Inc.           ****************/
/***************  Programmer : Joseph Lin              ****************/
/***************               Yih-Shin Weng           ****************/
/**********************************************************************/

#define _C_INIT_

#include "general.h"
//#include "flash.h"
#include "servopin.h"

#pragma NOAREGS

#if (defined(MT1389_REV_P) ||defined(MT1389_REV_K))
#ifdef USE_FLASH_90NS
  #define DMPLL2_CLK     0x13
#else
  #define DMPLL2_CLK     0x33
#endif

#define DMPLL2C_BAND     360
#define DMPLL2C_HI       0x02
#define DMPLL2C_LO       0x18
#define DEF_8032_CLK       20
#endif

BYTE code _pbCodeInfo[18] _at_ CODE_INFO_START_ADDRESS;

#ifdef DMPLL_NEW_METHOD
extern WORD wGetSysClk(void);
#endif /* DMPLL_NEW_METHOD */

/***************************************************************************
     Function : InitTimer(void)
  Dsecription : initial timers
    Parameter : None
       Return : None
***************************************************************************/
void InitTimer(void)
{
  /*  External Interrupt */
  TCON = INT0_LEVEL + INT1_LEVEL; // Int0, level trigger, Int1, level trigger
  MMainIntPTHigh();               // Decoder Int (int1) in Low Priority

#ifdef USING_TIMER0_CNT
  /*  Timer 0 Setting */
  TF0 = 0;
  TH0=0xFF;                       // 2ms// (65536-470) DIV 256,Reset Timer0
  TL0=0xFF;                       // (65536-470) MOD 256,Reset Timer0
#endif

  /*  Timer 1 Setting */
  TL1 = T2MSL;                   // Timer 1 sample time = 2 ms
  TH1 = T2MSH;
  // Timer0/1 configure as 16-bit timer
  TMOD = TM0MODE1 + TM0TIMER + TM1MODE1 + TM1TIMER;
  MTimer0PTLow();                 // Priority = 0
  MTimer1PTLow();                 // Priority = 0

  /* Timer 2 Setting */
  RCAP2L = TL2 = T2MSL ;         // Timer 2 sample time = 2 ms
  RCAP2H = TH2 = T2MSH ;
  T2CON = TM2TIMER + TM2MODE0 ;   // Timer 2 is 16-bit autoload timer
  MTimer2PTLow();                 // Priority = 0;

  // for 20ms Timer
  _bCnt20ms = TIEMR_20MS_CNT;
#if (defined(HYNIX_VFD) || defined(TMP86_VFD))
  _bVfdWorkCnt = 0;
#endif /* HYNIX_VFD || TMP86_VFD */
}

/***************************************************************************
     Function : void ClkInit(void)
  Dsecription : Initial clocks
    Parameter : None
       Return : None
***************************************************************************/
void ClkInit(void)
{
#if (defined(DMPLL_NEW_METHOD))
  WORD  wClk;
#endif

#if !(defined(MT1389_REV_P)||defined(MT1389_REV_K))
  WriteBIM(BIM_APLLC3, APLLC3_SETTING);
#ifdef USE_FLASH_70NS
  WriteBIM(BIM_DMPLL2, 0x33);
#else
  WriteBIM(BIM_DMPLL2, 0x13);
#endif  
#else
#ifndef DMPLL_NEW_METHOD
  WriteBIM(BIM_DMPLL2, DMPLL2_CLK);

  if (((WORD)(250 + DMPLL2_CLK * 2)) <= DMPLL2C_BAND)
    WriteBIM(BIM_DM2C, DMPLL2C_LO);
  else
    WriteBIM(BIM_DM2C, DMPLL2C_HI);
#endif
#endif

  // system clock setting is moved to DRAMInit()

  WriteBIM(BIM_XCKC, XCKC_SETTING);

#if !(defined(MT1389_REV_P) ||defined(MT1389_REV_K))
 WriteBIM(BIM_PCLKC, PC_27M);
#else
#ifdef DMPLL_NEW_METHOD
  WriteBIM(BIM_PLLS, PS_8032_CLK);
  WriteBIM(BIM_PLLD, ((wGetSysClk() / 2 / DEF_8032_CLK) - 1));
  WriteBIM(BIM_PCLKC, PC_DPL_CNTR);
#else
  WriteBIM(BIM_PCLKC, PC_DPL2D16); //Max'0407'2004, 8032 clock is DMPLL2/16, that is 352/16 = 22M,
                                   //before enable the dual-fetch mode.
#endif
#endif //MT1389_REV_P

#ifdef MT1389P_TCON
  WriteBIM(BIM_PLLS, PS_VPLL_6);
  WriteBIM(BIM_PLLD, 0x00);
  #ifdef DIGITAL_PANEL_32M
//digital panel 33.2Mhz
    WriteBIM(BIM_PLLS, 0x10);
    WriteBIM(BIM_PLLD, 0x19);
    
    WriteBIM(BIM_PLLS, 0x11);
    WriteBIM(BIM_PLLD, 0xC0);
    
    WriteBIM(BIM_PLLS, 0x32);
    WriteBIM(BIM_PLLD, 0x00);
  #endif
#endif

#ifdef MT1389_REV_P
  WriteBIM(BIM_PLLS, PS_ATA_CLK);  // Power-Down ATA 
  WriteBIM(BIM_PLLD, 0x80);

  WriteBIM(BIM_PLLS, PS_SFI_CLK);  // Power-Down SFI
  WriteBIM(BIM_PLLD, 0x80);

  WriteBIM(BIM_PLLS, PS_TVD_CLK);  // Power-Down TVD
  WriteBIM(BIM_PLLD, 0x80);

  WriteBIM(BIM_PLLS, PS_VDOIN_CLK);  // Power-Down VDOIN Clock 
  WriteBIM(BIM_PLLD, 0x80);    

  WriteBIM(BIM_PLLS, PS_TS_DEMUX_CLK);  // Power-Down DVBT 
  WriteBIM(BIM_PLLD, 0x80);

  WriteBIM(BIM_PLLS, PS_SC_CLK);  // Power-Down Smart Card 
  WriteBIM(BIM_PLLD, 0x80);
#endif

}

/************************************************************************
     Function : void ADSPInit(void)
  Description : Audio DSP initial
    Parameter : None
    Return    : None
************************************************************************/
void ADSPInit(void)
{
  WriteAUD(AUD_ADSPSEL, 0x02);
#ifdef AUDIO_LR_INV
  #ifdef AUDIO_DATA_I2S
    WriteAUD(AUD_AOUTCFG, 0xF2);  //I2S
  #elif defined(AUDIO_DATA_LTJ)
    WriteAUD(AUD_AOUTCFG, 0x62);  //Left-Justified
  #else // AUDIO_DATA_RTJ
    WriteAUD(AUD_AOUTCFG, 0x42);  //Right-Justified
  #endif // AUDIO_DATA_RTJ
#else // Standard Format
  #ifdef AUDIO_DATA_I2S
    WriteAUD(AUD_AOUTCFG, 0x72);  //I2S
  #elif defined(AUDIO_DATA_LTJ)
    WriteAUD(AUD_AOUTCFG, 0xE2);  //Left-Justified
  #else // AUDIO_DATA_RTJ
      WriteAUD(AUD_AOUTCFG, 0xC2);  //Right-Justified
  #endif // AUDIO_DATA_RTJ
#endif // Standard Format

#ifdef AUDIO_POLARITY_NINV
  #ifdef AUDIO_DATA_16BIT
    WriteAUD(AUD_ADACCFG, 0x10);  //16-Bit
  #elif defined(AUDIO_DATA_18BIT)
    WriteAUD(AUD_ADACCFG, 0x12);  //18-Bit
  #elif defined(AUDIO_DATA_20BIT)
    WriteAUD(AUD_ADACCFG, 0x14);  //20-Bit
  #else
    WriteAUD(AUD_ADACCFG, 0x18);  //24-Bit
  #endif
#else //External OP are odd stages.
  #ifdef AUDIO_DATA_16BIT
    WriteAUD(AUD_ADACCFG, 0x50);  //16-Bit
  #elif defined(AUDIO_DATA_18BIT)
    WriteAUD(AUD_ADACCFG, 0x52);  //18-Bit
  #elif defined(AUDIO_DATA_20BIT)
    WriteAUD(AUD_ADACCFG, 0x54);  //20-Bit
  #else
    WriteAUD(AUD_ADACCFG, 0x58);  //24-Bit
  #endif
#endif

#ifdef _INTACLK_
  #ifdef  AUDIO_256FS
  WriteAUD(AUD_ACLKCFG, 0x42); //Setting the Audio Clk to Internal Clk
  #else // AUDIO_384FS
      WriteAUD(AUD_ACLKCFG, 0x63); //Setting the Audio Clk to Internal Clk
  #endif
#else
  #ifdef  AUDIO_256FS
  WriteAUD(AUD_ACLKCFG, 0x52); //Setting the Audio Clk to External Clk
  #else // AUDIO_384FS
  WriteAUD(AUD_ACLKCFG, 0x73); //Setting the Audio Clk to External Clk
  #endif
#endif
  WriteAUD(AUD_IECCFG, 0x24);  //Enlarge the driving current to 4mA, and disable IEC output
  WriteAUD(AUD_BSCFG, 0x00);
  WriteAUD(AUD_MPINCFG, 0xB1);

#ifdef SUPPORT_SACD
  WriteAUD(AUD_MPINCFG1, SDATA5_SEL_SPBCK); // sdata5 of DSD will be output from SPBCK 
#endif
#ifdef MT1379
  WriteAUD(AUD_SPLIN0, 0);
  WriteAUD(AUD_SPLIN1, 0);
  WriteBIM(BIM_PCTL4, LINE_IN_SPDATA);    // set spdif/line-in same pin
#endif
}

/***************************************************************************
     Function : void RISCBootSetting(void)
  Dsecription : RISC boot setting
    Parameter : None
       Return : None
***************************************************************************/
void RISCBootSetting(void)
{
#if (defined(MT1389_REV_P) || defined(MT1389_REV_K))
  BYTE bVbiSet;
  WORD wInit ;

  // 20050510, init all shareinfo
  for (wInit = 0; wInit < (WORD)(SHARED_INFO_GRP_NS*SHARED_INFO_GRP_SIZE); wInit++)
    vSetSharedInfo(wInit, 0) ;
#endif

  // tell RISC DRAM config
#if (DRAM_SZ == DRAM_2M)
  vSetSharedInfo(SI_DRAM_CFG, SV_DRAM_2M);
#elif (DRAM_SZ == DRAM_4M)
  vSetSharedInfo(SI_DRAM_CFG, SV_DRAM_4M);
#elif (DRAM_SZ == DRAM_8M)
  vSetSharedInfo(SI_DRAM_CFG, SV_DRAM_8M);
#elif (DRAM_SZ == DRAM_16M)
  vSetSharedInfo(SI_DRAM_CFG, SV_DRAM_16M);
#endif

  if (bReadDEC(RW_RBCR1) & BWSEL_32) // 32 bits DRAM
  {
    vSetSharedInfo(SI_DRAM_BW, SV_DRAM_32BIT);
  }
  else // 16 bits DRAM
  {
    vSetSharedInfo(SI_DRAM_BW, SV_DRAM_16BIT);
  }

  // tell RISC flash config
#if (FLASH_SZ == 0)
  vSetSharedInfo(SI_FLASH_CFG, SV_FLASH_512K);
#elif (FLASH_SZ == 1)
  vSetSharedInfo(SI_FLASH_CFG, SV_FLASH_1M);
#elif (FLASH_SZ == 2)
  vSetSharedInfo(SI_FLASH_CFG, SV_FLASH_2M);
#endif

  // tel RISC servo boot initial status
  if (_testbit_(_fgPowerOnEject))
  {
    vSetSharedInfo(SI_SRV_BOOT_STATE, SV_SRV_BOOT_EJECT);
  }
  else if (_testbit_(_fgDiscUpgradeRestart))
  {
    vSetSharedInfo(SI_SRV_BOOT_STATE, SV_SRV_BOOT_UPG);
  }
  else /* default state */
  {
    // after loading user's configuration, we will change this state
    // according to player function
    vSetSharedInfo(SI_SRV_BOOT_STATE, SV_SRV_BOOT_LOAD);
  }

#ifdef RISC_1K_SQUARE_WAVE
  vSetSharedInfo(SI_SQUARE_WAVE_SET_VAL, 1);
#else
  vSetSharedInfo(SI_SQUARE_WAVE_SET_VAL, 0);
#endif

#ifdef MTK_TVE // for 1379 internal TVE
  vSetSharedInfo(SI_TVE_MODE, SV_INT_TVE);
  TVEInit();  // internal TV encoder setting
#else         // for external TVE only
  #ifdef  ENCODER_MASTER
  vSetSharedInfo(SI_TVE_MODE, SV_EXT_TVE_MASTER);
  #else
  vSetSharedInfo(SI_TVE_MODE, SV_EXT_TVE_SLAVE);
  #endif
#endif /* for external TVE only */

  vSetSharedInfo(SI_OSD_WB_NS, WB_INDEX_MAX);

//G.T1129:Port from 89L, MT1389K has no ROM code, so we can mark this.
#if !(defined( ROM_CODE_IN_DRAM) ||defined(MT1389_REV_P) ||defined(MT1389_REV_K))
  WriteBIM(BIM_PLLS, PS_ROM_NC_ADDR);
  WriteBIM(BIM_PLLD, 0xFF);
  WriteBIM(BIM_PLLS, PS_ROM_C_ADDR);
  WriteBIM(BIM_PLLD, 0x02);
  WriteBIM(BIM_PLLS, PS_ROM_DELAY_SEL);
  WriteBIM(BIM_PLLD, 0x17);
#ifndef MT1389_REV_K
  WriteBIM(BIM_PLLS, PS_CMN_CODE_CTRL);
//  WriteBIM(BIM_PLLD, 0x60);
  WriteBIM(BIM_PLLD, (0x60|bReadBIM(BIM_PLLD)));		// Modify
#endif
#endif  // MT1389_REV_E

}

/***************************************************************************
     Function : void RISCInit(void)
  Dsecription : Initial RISC
    Parameter : None
       Return : None
***************************************************************************/
void RISCInit(void)
{
  // make sure all used variables are not in XDATA
  DWRD dAddr;

#ifdef RS232_LOG
  DBGLogS("RISCInit start.\n");
#endif

#ifndef RISC_ICE_MODE
  #ifdef USE_FLASH_DMA
  MoveRISCCode();               // move the RISC code
  #endif
#endif

  //initial mapping done here
  WriteBIM(BIM_FCBA, (FLASH_CACH_BASE_ADDRESS >> 20) & 0xFF);
  WriteBIM(BIM_FNBA, (FLASH_NONCACH_BASE_ADDRESS >> 20) & 0xFF);
  WriteBIM(BIM_ACBA, (DRAMA_CACH_BASE_ADDRESS >> 20) & 0xFF);
  WriteBIM(BIM_ANBA, (DRAMA_NONCACH_BASE_ADDRESS >> 20) & 0xFF);
#ifndef RISC_ICE_MODE
  WriteBIM(BIM_BCBA, (DRAMB_CACH_BASE_ADDRESS >> 20) & 0xFF);
  WriteBIM(BIM_BNBA, (DRAMB_NONCACH_BASE_ADDRESS >> 20) & 0xFF);
#else
  WriteBIM(BIM_BCBA, (DRAMB_NONCACH_BASE_ADDRESS >> 20) & 0xFF);
  WriteBIM(BIM_BNBA, (DRAMB_CACH_BASE_ADDRESS  >> 20) & 0xFF);
#endif
  WriteBIM(BIM_IOBA, (IO_BASE_ADDRESS >> 20) & 0xFF);

  WriteBIM(BIM_DPAH, (DRAM_PARTITION_ADDR >> 16) & 0xFF);
  WriteBIM(BIM_DPAM, (DRAM_PARTITION_ADDR >> 8) & 0xFF);
  WriteBIM(BIM_DPAL, DRAM_PARTITION_ADDR & 0xFC);

  // assign RISC flash start offset
  if (bReadBIM(BIM_STAT) & ICEM) /* for 8032 ICE */
  {
    SetBitBIM(BIM_PCTL1, ADDR_LOCK);    // lock A16, A17
    ClrBitBIM(BIM_IODOM, IOM_BMASK);    // switch to bank 0

    SwitchToROM();
#ifdef RISC_ICE_MODE
    bHiByte(wHiWord(dAddr)) = 0;
    bLoByte(wHiWord(dAddr)) = XBYTE[CODE_INFO_START_ADDRESS + 14]; // little endian
    bHiByte(wLoWord(dAddr)) = XBYTE[CODE_INFO_START_ADDRESS + 13];
    bLoByte(wLoWord(dAddr)) = XBYTE[CODE_INFO_START_ADDRESS + 12];
    dAddr -= (DWRD)(307200);
#else
    bHiByte(wHiWord(dAddr)) = 0;
    bLoByte(wHiWord(dAddr)) = XBYTE[CODE_INFO_START_ADDRESS + 2]; // little endian
    bHiByte(wLoWord(dAddr)) = XBYTE[CODE_INFO_START_ADDRESS + 1];
    bLoByte(wLoWord(dAddr)) = XBYTE[CODE_INFO_START_ADDRESS + 0];
#endif
    SwitchToREG();
  }
  else
  {
    bHiByte(wHiWord(dAddr)) = 0;
    bLoByte(wHiWord(dAddr)) = _pbCodeInfo[2]; // little endian
    bHiByte(wLoWord(dAddr)) = _pbCodeInfo[1];
    bLoByte(wLoWord(dAddr)) = _pbCodeInfo[0];
  }

  dAddr = dAddr >> 2;
  WriteBIM(BIM_FOFFH, bHiByte(wLoWord(dAddr)));
  WriteBIM(BIM_FOFFL, bLoByte(wLoWord(dAddr)));
#ifdef MT1379
  WriteBIM(BIM_FOFFS, bLoByte(wHiWord(dAddr)));
#endif
  vSetSharedInfo(SI_FLASH_OFFSET_HI, bLoByte(wHiWord(dAddr)));
  vSetSharedInfo(SI_FLASH_OFFSET_MID, bHiByte(wLoWord(dAddr)));
  vSetSharedInfo(SI_FLASH_OFFSET_LO, bLoByte(wLoWord(dAddr)));

  // tell RISC where is the captured logo, absolute byte address
#ifdef SUPPORT_CAPTURE_LOGO
  #if (FLASH_SZ == 2)
    dAddr = 0x200000;
  #else  // default is 1
    dAddr = 0x100000;
  #endif


  #if (CAP_LOGO_SZ == SV_CAP_LOGO_SZ_64K)
    dAddr -= ((DWRD)64 * 1024);
  #elif (CAP_LOGO_SZ == SV_CAP_LOGO_SZ_128K)
    dAddr -= ((DWRD)128 * 1024);
  #elif (CAP_LOGO_SZ == SV_CAP_LOGO_SZ_64K_CPPM)
    dAddr -= ((DWRD)64 * 1024);
  #elif (CAP_LOGO_SZ == SV_CAP_LOGO_SZ_128K_CPPM)
    dAddr -= ((DWRD)128 * 1024);
  #endif

  #ifdef CAP_LOGO_CPPM_NOT_OVERLAP
    dAddr -= 0x10000;
  #endif

  dAddr = dAddr & 0xFF0000;
  vSetSharedInfo(SI_CAP_LOGO_SA_H, bLoByte(wHiWord(dAddr)));
  vSetSharedInfo(SI_CAP_LOGO_SA_M, 0x00);
  vSetSharedInfo(SI_CAP_LOGO_SA_L, 0x00);
#endif /* SUPPORT_CAPTURE_LOGO */

#ifdef MT1379_REV_C
  WriteBIM(BIM_DRVC, 0x09);             // driving strength, at least 4mA for Rev.C
#else
  WriteBIM(BIM_DRVC, 0x00);             // driving strength
#endif
  WriteBIM(BIM_DUAL, DUALEN + CPU_HALF_EN);           // enable the dual-fetch mode

  // enable Base address
  WriteBIM(BIM_ADDREN, FAEN+FNEN+DACEN+DANEN+DBCEN+DBNEN+IOEN);

#ifdef RISC_ICE_MODE
  WriteBIM(BIM_STAT, 0x01);     // enable RISC ICE
#else
  #ifndef USE_FLASH_DMA
  MoveRISCCode();               // move the RISC code
  #endif
#endif

#ifdef RISC_PROTECT_EN
  SetBitDEC(RW_RAMPC, RCPT);
#endif


#ifdef RS232_LOG
  DBGLogS("RISCInit ok.\n");
#endif
}

/************************************************************************
     Function : void InitSharedReg(void)
  Description : clear all shared register
    Parameter : None
    Return    : None
************************************************************************/
void InitSharedReg(void)
{
  BYTE bIdx;

  for (bIdx = 0; bIdx < 16; bIdx++)
  {
    vSetSharedReg(bIdx, 0);
  }
}

/************************************************************************
     Function : void TVEInit(void)
  Description : TV Encoder initial
    Parameter : None
    Return    : None
************************************************************************/
void TVEInit(void)
{
  BYTE bTvMisc;

#ifdef MT1379 // for 1379 internal TVE
#if defined(MT1379_MANUFACTURE_TEST)
  vSetSharedInfo(SI_TVE_OUT_MODE, SV_TVE_YCBCR);
#else
  vSetSharedInfo(SI_TVE_OUT_MODE, SV_TVE_DIRECT);
#endif
  vSetSharedInfo(SI_PSCAN_EN, SV_OFF);
  vSetSharedInfo(SI_PSCAN_MODE, SV_PSCAN_AUTO);
  vSetSharedInfo(SI_PSCAN_VIDEO, PSCAN_DEFAULT_VIDEO_MODE);
  // for 1379 video in
  vSetSharedInfo(SI_VDO_IN_EN, SV_VDO_IN_OFF);
  vSetSharedInfo(SI_VDO_IN_SCALE, SV_VDO_IN_1);
#endif

#ifdef HVSYNC_ON_GPIO_PIN
     vSetSharedInfo(SI_HV_SYNC_ENABLE, (1<<6)|SV_HVSYNC_ON_GPIO_PIN);
#else
    vSetSharedInfo(SI_HV_SYNC_ENABLE, 0); //kenny initialize this shareinfo to set for 89S
#endif

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