adder4.v

来自「加法器的V代码,这个源代码已经经过严格的检查」· Verilog 代码 · 共 68 行

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    16:13:08 03/19/2009 
// Design Name: 
// Module Name:    adder4 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module adder4(cout,sum);
output[3:0] sum;
output cout;
wire [3:0] ina,inb;
wire cin;
wire [35:0]control0;
wire [13:0] async_in;
wire [8:0] async_out;
icon i_icon
    (
      .control0(control0)
    );
vio i_vio
    (
      .control(control0),
      .async_in(async_in),
      .async_out(async_out)
    );
assign async_in[3:0]=ina[3:0];
assign async_in[7:4]=inb[3:0];
assign async_in[8]=cin;
assign async_in[12:9]=sum[3:0];
assign async_in[13]=cout;
assign ina[3:0]=async_out[3:0];
assign inb[3:0]=async_out[7:4];
assign cin=async_out[8];
assign {cout,sum}=ina+inb+cin;
endmodule

module icon 
  (
      control0
  );
  output [35:0] control0;
endmodule
module vio
  (
    control,
    async_in,
    async_out
  );
  input  [35:0] control;
  input  [13:0] async_in;
  output [8:0] async_out;
endmodule