mem_test.vhd

It is the code for implementing the project titled "The Reconfigurable Instruction Cell Array(IEEE 2

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
-- use package
USE work.procmem_definitions.ALL;
-------------------------------------------------------------------------------
ENTITY t_memory IS
END t_memory;
-------------------------------------------------------------------------------
ARCHITECTURE tbench OF t_memory IS
COMPONENT memory IS
PORT (
clk : IN STD_ULOGIC;
rst_n : IN STD_ULOGIC;
MemRead : IN STD_ULOGIC;
MemWrite : IN STD_ULOGIC;
mem_address : IN STD_ULOGIC_VECTOR(width-1 DOWNTO 0);
data_in : IN STD_ULOGIC_VECTOR(width-1 DOWNTO 0);
data_out : OUT STD_ULOGIC_VECTOR(width-1 DOWNTO 0) );
END COMPONENT;
-- component ports
SIGNAL clk : STD_ULOGIC;
SIGNAL rst_n : STD_ULOGIC;
SIGNAL MemRead : STD_ULOGIC;
SIGNAL MemWrite : STD_ULOGIC;
SIGNAL mem_address : STD_ULOGIC_VECTOR(width-1 DOWNTO 0);
SIGNAL data_in : STD_ULOGIC_VECTOR(width-1 DOWNTO 0);
SIGNAL data_out : STD_ULOGIC_VECTOR(width-1 DOWNTO 0);
-- definition of a clock period
CONSTANT period : time := 10 ns;
-- switch for clock generator
SIGNAL clken_p : boolean := true;
-- STD_ULOGIC_VECTOR TO STRING
FUNCTION TO_string(arg : std_ulogic_vector) RETURN string IS
ALIAS u : STD_ULOGIC_VECTOR(arg'length DOWNTO 1) IS arg;
VARIABLE result : string(arg'length DOWNTO 1);
BEGIN
FOR i IN u'range LOOP
CASE u(i) IS
WHEN 'U' => result(i) := 'U';
WHEN 'X' => result(i) := 'X';
WHEN '0' => result(i) := '0';
WHEN '1' => result(i) := '1';
WHEN 'Z' => result(i) := 'Z';
WHEN 'W' => result(i) := 'W';
WHEN 'L' => result(i) := 'L';
WHEN 'H' => result(i) := 'H';
WHEN '-' => result(i) := '-';
END CASE;
END LOOP;
RETURN result;
END TO_string;
-- UNSIGNED TO STRING
FUNCTION TO_string(arg : unsigned) RETURN string IS
ALIAS u : unsigned(arg'length DOWNTO 1) IS arg;
VARIABLE result : string(arg'length DOWNTO 1);
BEGIN
FOR i IN u'range LOOP
CASE u(i) IS
WHEN 'U' => result(i) := 'U';
WHEN 'X' => result(i) := 'X';
WHEN '0' => result(i) := '0';
WHEN '1' => result(i) := '1';
WHEN 'Z' => result(i) := 'Z';
WHEN 'W' => result(i) := 'W';
WHEN 'L' => result(i) := 'L';
WHEN 'H' => result(i) := 'H';
WHEN '-' => result(i) := '-';

END CASE;
END LOOP;
RETURN result;
END TO_string;
BEGIN -- tbench
-- component instantiation
DUT: memory
PORT MAP (
clk => clk,
rst_n => rst_n,
MemRead => MemRead,
MemWrite => MemWrite,
mem_address => mem_address,
data_in => data_in,
data_out => data_out );
-- clock generation
clock_proc : PROCESS
BEGIN
WHILE clken_p LOOP
clk <= '0'; WAIT FOR period/2;
clk <= '1'; WAIT FOR period/2;
END LOOP;
WAIT;
END PROCESS;
-- reset generation
reset : rst_n <= '0', '1' AFTER period;
-- waveform generation
WaveGen_Proc : PROCESS
VARIABLE mem_temp : STD_ULOGIC_VECTOR(width-1 DOWNTO 0);
TYPE array_vector IS ARRAY (0 TO 5) OF
STD_ULOGIC_VECTOR(width-1 DOWNTO 0);
VARIABLE addr_pattern : array_vector;
VARIABLE data_pattern : array_vector;
BEGIN
-- initialization
MemRead <= '1';
MemWrite <= '0';
mem_address <= (OTHERS => '0');
-- addr_pattern
addr_pattern := ( -- block: 3, 2, 1, 0
x"00000000", -- use correct word address
x"00000004",
x"00000008",
x"0000000C",
x"00000010",
x"00000014");
data_pattern := ( -- data arises every byte
x"01020304",
x"05060708",
x"090A0B0C",
x"0D0E0F10",
x"11121314",
x"15161718");
-- reset
WAIT FOR period;
-- write pattern to mem
MemRead <= '0';
MemWrite <= '1';
FOR i in data_pattern'RANGE LOOP
data_in <= data_pattern(i);
mem_address <= addr_pattern(i);
WAIT FOR period;
END LOOP;
-- read memory and compare with pattern

MemRead <= '1';
MemWrite <= '0';
FOR k in data_pattern'RANGE LOOP
mem_address <= addr_pattern(k);
WAIT FOR period;
ASSERT data_out = data_pattern(k)
REPORT "p.no. " & TO_STRING(TO_UNSIGNED(k, data_pattern'LENGTH-1)) & lf
& "act. address: " & lf & TO_STRING(mem_address) & lf
& "actual value: " & lf & TO_STRING(data_out) & lf
& "expected value: " & lf & TO_STRING(data_pattern(k))
SEVERITY note;
END LOOP;
WAIT FOR period;
clken_p <= false;
WAIT;
END PROCESS WaveGen_Proc;
END tbench;