t_procmem_init.vhd

It is the code for implementing the project titled "The Reconfigurable Instruction Cell Array(IEEE 2

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
-- use package
USE work.procmem_definitions.ALL;
-------------------------------------------------------------------------------
ENTITY t_procmem_init IS
END t_procmem_init;
-------------------------------------------------------------------------------
ARCHITECTURE tbench OF t_procmem_init IS
COMPONENT mips
PORT (
clk, rst_n : IN std_ulogic;
mem_data : IN std_ulogic_vector(width-1 downto 0);
reg_B, mem_address : OUT std_ulogic_vector(width-1 downto 0);
MemRead, MemWrite : OUT std_ulogic);
END COMPONENT;
COMPONENT memory
PORT (
clk : IN STD_ULOGIC;
rst_n : IN STD_ULOGIC;
MemRead : IN STD_ULOGIC;
MemWrite : IN STD_ULOGIC;
mem_address : IN STD_ULOGIC_VECTOR(width-1 DOWNTO 0);
data_in : IN STD_ULOGIC_VECTOR(width-1 DOWNTO 0);
data_out : OUT STD_ULOGIC_VECTOR(width-1 DOWNTO 0));
END COMPONENT;
-- component ports
SIGNAL clk : STD_ULOGIC;
SIGNAL rst_n : STD_ULOGIC;
SIGNAL mem_data : std_ulogic_vector(width-1 downto 0);
signal reg_B : std_ulogic_vector(width-1 downto 0);
signal mem_address : std_ulogic_vector(width-1 downto 0);
signal MemRead : std_ulogic;
signal MemWrite : std_ulogic;
SIGNAL mem_data_ini : std_ulogic_vector(width-1 downto 0);
signal reg_B_ini : std_ulogic_vector(width-1 downto 0);
signal mem_address_ini : std_ulogic_vector(width-1 downto 0);
signal MemRead_ini : std_ulogic;
signal MemWrite_ini : std_ulogic;
SIGNAL mem_data_mux : std_ulogic_vector(width-1 downto 0);
signal reg_B_mux : std_ulogic_vector(width-1 downto 0);
signal mem_address_mux : std_ulogic_vector(width-1 downto 0);
signal MemRead_mux : std_ulogic;
signal MemWrite_mux : std_ulogic;
-- definition of a clock period
CONSTANT period : time := 10 ns;
-- switch for clock generator
SIGNAL clken_p : boolean := true;
BEGIN -- tbench
inst_mips : mips
PORT MAP (
clk => clk,
rst_n => rst_n,
mem_data => mem_data_mux,
reg_B => reg_B,
mem_address => mem_address,
MemRead => MemRead,
MemWrite => MemWrite
);
inst_memory : memory
PORT MAP (
clk => clk,
rst_n => rst_n,
MemRead => MemRead_mux,
MemWrite => MemWrite_mux,
mem_address => mem_address_mux,
data_in => reg_B_mux,
data_out => mem_data
);
-- clock generation
clock_proc : PROCESS
BEGIN
WHILE clken_p LOOP
clk <= '0'; WAIT FOR period/2;
clk <= '1'; WAIT FOR period/2;
END LOOP;
WAIT;
END PROCESS;
-- reset generation
-- not used because of initialisation during explicit reset
--reset : rst_n <= '0', '1' AFTER period;
-- multiplexer for memory initialization signals,
-- because there is only one driver allowed at each signal
mux : PROCESS(rst_n, MemWrite_ini, MemRead_ini, mem_data_ini, reg_B_ini,
mem_address_ini,
MemWrite, MemRead, mem_data, reg_B, mem_address)
BEGIN
IF rst_n = '0' THEN
MemWrite_mux <= MemWrite_ini;
MemRead_mux <= MemRead_ini;
mem_data_mux <= mem_data_ini;
reg_B_mux <= reg_B_ini;
mem_address_mux <= mem_address_ini;
ELSE
MemWrite_mux <= MemWrite;
MemRead_mux <= MemRead;
mem_data_mux <= mem_data;
reg_B_mux <= reg_B;
mem_address_mux <= mem_address;
END IF;
END PROCESS;
-- waveform generation
WaveGen_Proc : PROCESS
VARIABLE mem_temp : STD_ULOGIC_VECTOR(width-1 DOWNTO 0);
TYPE array_vector IS ARRAY (0 TO 15) OF
STD_ULOGIC_VECTOR(width-1 DOWNTO 0);
VARIABLE addr_pattern : array_vector;
VARIABLE data_pattern : array_vector;
BEGIN
-- pattern needed for memory initialisation at the beginning
addr_pattern := (
x"00000000",
x"00000004",
x"00000008",
x"0000000C",
x"00000010",
x"00000014",
x"00000018",
x"0000001C",
x"00000020",
x"00000024",
x"00000028",
x"0000002C",
x"00000030",
x"00000038",
x"00000080",
x"00000084"
);
data_pattern := (

"10001100000100000000000010000000",
"10001100000100010000000010000100",
"00000010000100011001000000100000",
"10101100000100100000000010001000",
"00000010001100001001100000100010",
"10101100000100110000000010001100",
"00000010001100001010000000100100",
"10101100000101000000000010010000",
"00000010001100001010100000100101",
"10101100000101010000000010010100",
"00000010000100011011000000101010",
"10101100000101100000000010011000",
"00010010000101000000000000000001",
"00001000000000000000000000000010",
"00000000000000000000000101111011",
"00000000000000000000000101111111");
-- explicit reset
rst_n <= '0';
-- initialize memory output
mem_data_ini <= (OTHERS => '0');
-- write pattern to mem
MemWrite_ini <= '1';
MemRead_ini <= '0';
FOR i in data_pattern'RANGE LOOP
reg_B_ini <= data_pattern(i);
mem_address_ini <= addr_pattern(i);
WAIT FOR period;
END LOOP;
-- set signals to zero before quitting initialisation
WAIT FOR period;
MemWrite_ini <= '0';
MemRead_ini <= '0';
reg_B_ini <= (OTHERS => '0');
mem_address_ini <= (OTHERS => '0');
mem_data_ini <= (OTHERS => '0');
WAIT FOR 2*period;
-- start
rst_n <= '1';
-- wait for results
WAIT FOR 100*period;
clken_p <= false;
WAIT;
END PROCESS WaveGen_Proc;
END tbench;