t_procmem.vhd

来自「It is the code for implementing the proj」· VHDL 代码 · 共 50 行

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE work.procmem_definitions.ALL;
-------------------------------------------------------------------------------
ENTITY t_procmem IS
END t_procmem;
-------------------------------------------------------------------------------
ARCHITECTURE tbench OF t_procmem IS
COMPONENT procmem IS
PORT (
clk, rst_n : IN STD_ULOGIC
);
END COMPONENT;
-- component ports
SIGNAL clk : STD_ULOGIC;
SIGNAL rst_n : STD_ULOGIC;
-- definition of a clock period
CONSTANT period : time := 10 ns;
-- switch for clock generator
SIGNAL clken_p : boolean := true;
BEGIN -- tbench
-- component instantiation
DUT: procmem
PORT MAP (
clk => clk,
rst_n => rst_n
);
-- clock generation
clock_proc : PROCESS
BEGIN
WHILE clken_p LOOP
clk <= '0'; WAIT FOR period/2;
clk <= '1'; WAIT FOR period/2;
END LOOP;
WAIT;
END PROCESS;
-- reset generation
reset : rst_n <= '0', '1' AFTER period;
-- waveform generation
WaveGen_Proc : PROCESS
BEGIN
-- reset
WAIT FOR period;
-- wait for results
WAIT FOR 25*period;
clken_p <= false;
WAIT;
END PROCESS WaveGen_Proc;
END tbench;