array.vhd

来自「It is the code for implementing the proj」· VHDL 代码 · 共 31 行

         
library IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity product is
port (ml,md:in std_logic_vector( 3 downto 0);
      result:out std_logic_vector(7 downto 0));
end product;

architecture product of product is

begin
  process(ml)
  variable  t,d:std_logic_vector(7 downto 0);
  begin
d:="00000000";
t:="00000000";
  while t < md loop
   d:=d + ml;
   t:=t+'1';
   end loop;
   result<=d;
   end process;
   
  end product;