📄 stm32f10x_tim.txt
字号:
AREA ||i.TIM_ITConfig||, CODE, READONLY, ALIGN=1
TIM_ITConfig PROC
;;;900
;;;901 if (NewState != DISABLE)
000000 2a00 CMP r2,#0
;;;902 {
;;;903 /* Enable the Interrupt sources */
;;;904 TIMx->DIER |= TIM_IT;
000002 8982 LDRH r2,[r0,#0xc]
000004 d001 BEQ |L21.10|
000006 430a ORRS r2,r2,r1
000008 e000 B |L21.12|
|L21.10|
;;;905 }
;;;906 else
;;;907 {
;;;908 /* Disable the Interrupt sources */
;;;909 TIMx->DIER &= (u16)~TIM_IT;
00000a 438a BICS r2,r2,r1
|L21.12|
00000c 8182 STRH r2,[r0,#0xc] ;904
;;;910 }
;;;911 }
00000e 4770 BX lr
;;;912
ENDP
AREA ||i.TIM_GenerateEvent||, CODE, READONLY, ALIGN=1
TIM_GenerateEvent PROC
;;;935 /* Set the event sources */
;;;936 TIMx->EGR = TIM_EventSource;
000000 8281 STRH r1,[r0,#0x14]
;;;937 }
000002 4770 BX lr
;;;938
ENDP
AREA ||i.TIM_DMAConfig||, CODE, READONLY, ALIGN=1
TIM_DMAConfig PROC
;;;966 /* Set the DMA Base and the DMA Burst Length */
;;;967 TIMx->DCR = TIM_DMABase | TIM_DMABurstLength;
000000 4311 ORRS r1,r1,r2
000002 f8a0f8a0 STRH r1,[r0,#0x48]
;;;968 }
000006 4770 BX lr
;;;969
ENDP
AREA ||i.TIM_DMACmd||, CODE, READONLY, ALIGN=1
TIM_DMACmd PROC
;;;995
;;;996 if (NewState != DISABLE)
000000 2a00 CMP r2,#0
;;;997 {
;;;998 /* Enable the DMA sources */
;;;999 TIMx->DIER |= TIM_DMASource;
000002 8982 LDRH r2,[r0,#0xc]
000004 d001 BEQ |L24.10|
000006 430a ORRS r2,r2,r1
000008 e000 B |L24.12|
|L24.10|
;;;1000 }
;;;1001 else
;;;1002 {
;;;1003 /* Disable the DMA sources */
;;;1004 TIMx->DIER &= (u16)~TIM_DMASource;
00000a 438a BICS r2,r2,r1
|L24.12|
00000c 8182 STRH r2,[r0,#0xc] ;999
;;;1005 }
;;;1006 }
00000e 4770 BX lr
;;;1007
ENDP
AREA ||i.TIM_InternalClockConfig||, CODE, READONLY, ALIGN=1
TIM_InternalClockConfig PROC
;;;1021 /* Disable slave mode to clock the prescaler directly with the internal clock */
;;;1022 TIMx->SMCR &= SMCR_SMS_Mask;
000000 8901 LDRH r1,[r0,#8]
000002 f021f021 BIC r1,r1,#7
000006 8101 STRH r1,[r0,#8]
;;;1023 }
000008 4770 BX lr
;;;1024 /*******************************************************************************
ENDP
AREA ||i.TIM_SelectInputTrigger||, CODE, READONLY, ALIGN=1
TIM_SelectInputTrigger PROC
000000 8902 LDRH r2,[r0,#8]
000002 f022f022 BIC r2,r2,#0x70
000006 430a ORRS r2,r2,r1
000008 8102 STRH r2,[r0,#8]
00000a 4770 BX lr
ENDP
AREA ||i.TIM_ITRxExternalClockConfig||, CODE, READONLY, ALIGN=1
TIM_ITRxExternalClockConfig PROC
;;;1312 /* Get the TIMx SMCR register value */
;;;1313 tmpsmcr = TIMx->SMCR;
000000 8902 LDRH r2,[r0,#8]
000002 f022f022 BIC r2,r2,#0x70
000006 430a ORRS r2,r2,r1
000008 8102 STRH r2,[r0,#8]
00000a 8901 LDRH r1,[r0,#8]
00000c f041f041 ORR r1,r1,#7
000010 8101 STRH r1,[r0,#8]
000012 4770 BX lr
ENDP
AREA ||i.TIM_TIxExternalClockConfig||, CODE, READONLY, ALIGN=1
TIM_TIxExternalClockConfig PROC
;;;1070 u16 TIM_ICPolarity, u16 ICFilter)
;;;1071 {
000000 b570 PUSH {r4-r6,lr}
000002 460d MOV r5,r1
000004 4611 MOV r1,r2
000006 4604 MOV r4,r0
;;;1072 /* Check the parameters */
;;;1073 assert_param(IS_TIM_123458_PERIPH(TIMx));
;;;1074 assert_param(IS_TIM_TIXCLK_SOURCE(TIM_TIxExternalCLKSource));
;;;1075 assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity));
;;;1076 assert_param(IS_TIM_IC_FILTER(ICFilter));
;;;1077
;;;1078 /* Configure the Timer Input Clock Source */
;;;1079 if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2)
000008 2d60 CMP r5,#0x60
;;;1080 {
;;;1081 TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
00000a f04ff04f MOV r2,#1
00000e d102 BNE |L28.22|
000010 f7fff7ff BL TI2_Config
000014 e001 B |L28.26|
|L28.22|
;;;1082 }
;;;1083 else
;;;1084 {
;;;1085 TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
000016 f7fff7ff BL TI1_Config
|L28.26|
00001a 8920 LDRH r0,[r4,#8]
00001c f020f020 BIC r0,r0,#0x70
000020 4328 ORRS r0,r0,r5
000022 8120 STRH r0,[r4,#8]
;;;1086 }
;;;1087
;;;1088 /* Select the Trigger source */
;;;1089 TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource);
;;;1090
;;;1091 /* Select the External clock mode1 */
;;;1092 TIMx->SMCR |= TIM_SlaveMode_External1;
000024 8920 LDRH r0,[r4,#8]
000026 f040f040 ORR r0,r0,#7
00002a 8120 STRH r0,[r4,#8]
;;;1093 }
00002c bd70 POP {r4-r6,pc}
;;;1094
ENDP
AREA ||i.TIM_ETRConfig||, CODE, READONLY, ALIGN=1
TIM_ETRConfig PROC
000000 b510 PUSH {r4,lr}
000002 8904 LDRH r4,[r0,#8]
000004 4311 ORRS r1,r1,r2
000006 b2e4 UXTB r4,r4
000008 ea41ea41 ORR r1,r1,r3,LSL #8
00000c 4321 ORRS r1,r1,r4
00000e 8101 STRH r1,[r0,#8]
000010 bd10 POP {r4,pc}
ENDP
AREA ||i.TIM_ETRClockMode1Config||, CODE, READONLY, ALIGN=1
TIM_ETRClockMode1Config PROC
;;;1116 u16 ExtTRGFilter)
;;;1117 {
000000 b510 PUSH {r4,lr}
000002 4604 MOV r4,r0
;;;1118 u16 tmpsmcr = 0;
;;;1119
;;;1120 /* Check the parameters */
;;;1121 assert_param(IS_TIM_123458_PERIPH(TIMx));
;;;1122 assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
;;;1123 assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
;;;1124 assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
;;;1125
;;;1126 /* Configure the ETR Clock source */
;;;1127 TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
000004 f7fff7ff BL TIM_ETRConfig
;;;1128
;;;1129 /* Get the TIMx SMCR register value */
;;;1130 tmpsmcr = TIMx->SMCR;
000008 8920 LDRH r0,[r4,#8]
;;;1131
;;;1132 /* Reset the SMS Bits */
;;;1133 tmpsmcr &= SMCR_SMS_Mask;
;;;1134 /* Select the External clock mode1 */
;;;1135 tmpsmcr |= TIM_SlaveMode_External1;
;;;1136
;;;1137 /* Select the Trigger selection : ETRF */
;;;1138 tmpsmcr &= SMCR_TS_Mask;
;;;1139 tmpsmcr |= TIM_TS_ETRF;
00000a f040f040 ORR r0,r0,#0x77
;;;1140
;;;1141 /* Write to TIMx SMCR */
;;;1142 TIMx->SMCR = tmpsmcr;
00000e 8120 STRH r0,[r4,#8]
;;;1143 }
000010 bd10 POP {r4,pc}
;;;1144
ENDP
AREA ||i.TIM_ETRClockMode2Config||, CODE, READONLY, ALIGN=1
TIM_ETRClockMode2Config PROC
;;;1166 u16 TIM_ExtTRGPolarity, u16 ExtTRGFilter)
;;;1167 {
000000 b510 PUSH {r4,lr}
000002 4604 MOV r4,r0
;;;1168 /* Check the parameters */
;;;1169 assert_param(IS_TIM_123458_PERIPH(TIMx));
;;;1170 assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
;;;1171 assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
;;;1172 assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
;;;1173
;;;1174 /* Configure the ETR Clock source */
;;;1175 TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
000004 f7fff7ff BL TIM_ETRConfig
;;;1176
;;;1177 /* Enable the External clock mode2 */
;;;1178 TIMx->SMCR |= SMCR_ECE_Set;
000008 8920 LDRH r0,[r4,#8]
00000a f440f440 ORR r0,r0,#0x4000
00000e 8120 STRH r0,[r4,#8]
;;;1179 }
000010 bd10 POP {r4,pc}
;;;1180
ENDP
AREA ||i.TIM_PrescalerConfig||, CODE, READONLY, ALIGN=1
TIM_PrescalerConfig PROC
;;;1244 /* Set the Prescaler value */
;;;1245 TIMx->PSC = Prescaler;
000000 8501 STRH r1,[r0,#0x28]
;;;1246
;;;1247 /* Set or reset the UG Bit */
;;;1248 TIMx->EGR = TIM_PSCReloadMode;
000002 8282 STRH r2,[r0,#0x14]
;;;1249 }
000004 4770 BX lr
;;;1250
ENDP
AREA ||i.TIM_CounterModeConfig||, CODE, READONLY, ALIGN=1
TIM_CounterModeConfig PROC
;;;1273
;;;1274 tmpcr1 = TIMx->CR1;
000000 8802 LDRH r2,[r0,#0]
;;;1275
;;;1276 /* Reset the CMS and DIR Bits */
;;;1277 tmpcr1 &= CR1_CounterMode_Mask;
000002 f240f240 MOV r3,#0x38f
000006 401a ANDS r2,r2,r3
;;;1278
;;;1279 /* Set the Counter Mode */
;;;1280 tmpcr1 |= TIM_CounterMode;
000008 430a ORRS r2,r2,r1
;;;1281
;;;1282 /* Write to TIMx CR1 register */
;;;1283 TIMx->CR1 = tmpcr1;
00000a 8002 STRH r2,[r0,#0]
;;;1284 }
00000c 4770 BX lr
;;;1285
ENDP
AREA ||i.TIM_EncoderInterfaceConfig||, CODE, READONLY, ALIGN=1
TIM_EncoderInterfaceConfig PROC
;;;1350 u16 TIM_IC1Polarity, u16 TIM_IC2Polarity)
;;;1351 {
000000 b570 PUSH {r4-r6,lr}
;;;1352 u16 tmpsmcr = 0;
;;;1353 u16 tmpccmr1 = 0;
;⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -