📄 stm32f10x_tim.txt
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ENDP
AREA ||i.TIM_PWMIConfig||, CODE, READONLY, ALIGN=1
TIM_PWMIConfig PROC
;;;650 void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
;;;651 {
000000 e92de92d PUSH {r4-r8,lr}
000004 460c MOV r4,r1
;;;652 u16 icoppositepolarity = TIM_ICPolarity_Rising;
000006 2500 MOVS r5,#0
;;;653 u16 icoppositeselection = TIM_ICSelection_DirectTI;
;;;654
;;;655 /* Check the parameters */
;;;656 assert_param(IS_TIM_123458_PERIPH(TIMx));
;;;657
;;;658 /* Select the Opposite Input Polarity */
;;;659 if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising)
000008 8849 LDRH r1,[r1,#2]
00000a 4607 MOV r7,r0 ;651
00000c 2601 MOVS r6,#1 ;653
00000e b901 CBNZ r1,|L13.18|
;;;660 {
;;;661 icoppositepolarity = TIM_ICPolarity_Falling;
000010 2502 MOVS r5,#2
|L13.18|
;;;662 }
;;;663 else
;;;664 {
;;;665 icoppositepolarity = TIM_ICPolarity_Rising;
;;;666 }
;;;667
;;;668 /* Select the Opposite Input */
;;;669 if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI)
000012 88a2 LDRH r2,[r4,#4]
000014 2a01 CMP r2,#1
000016 d100 BNE |L13.26|
;;;670 {
;;;671 icoppositeselection = TIM_ICSelection_IndirectTI;
000018 2602 MOVS r6,#2
|L13.26|
;;;672 }
;;;673 else
;;;674 {
;;;675 icoppositeselection = TIM_ICSelection_DirectTI;
;;;676 }
;;;677
;;;678 if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
00001a 8820 LDRH r0,[r4,#0]
00001c 8923 LDRH r3,[r4,#8]
00001e 2800 CMP r0,#0
;;;679 {
;;;680 /* TI1 Configuration */
;;;681 TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
000020 4638 MOV r0,r7
000022 d111 BNE |L13.72|
000024 f7fff7ff BL TI1_Config
;;;682 TIM_ICInitStruct->TIM_ICFilter);
;;;683
;;;684 /* Set the Input Capture Prescaler value */
;;;685 TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
000028 88e1 LDRH r1,[r4,#6]
00002a 4638 MOV r0,r7
00002c f7fff7ff BL TIM_SetIC1Prescaler
;;;686
;;;687 /* TI2 Configuration */
;;;688 TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
000030 8923 LDRH r3,[r4,#8]
000032 4632 MOV r2,r6
000034 4629 MOV r1,r5
000036 4638 MOV r0,r7
000038 f7fff7ff BL TI2_Config
;;;689
;;;690 /* Set the Input Capture Prescaler value */
;;;691 TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
00003c 88e1 LDRH r1,[r4,#6]
00003e 4638 MOV r0,r7
000040 e8bde8bd POP {r4-r8,lr}
000044 f7fff7ff B.W TIM_SetIC2Prescaler
|L13.72|
;;;692 }
;;;693 else
;;;694 {
;;;695 /* TI2 Configuration */
;;;696 TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
000048 f7fff7ff BL TI2_Config
;;;697 TIM_ICInitStruct->TIM_ICFilter);
;;;698
;;;699 /* Set the Input Capture Prescaler value */
;;;700 TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
00004c 88e1 LDRH r1,[r4,#6]
00004e 4638 MOV r0,r7
000050 f7fff7ff BL TIM_SetIC2Prescaler
;;;701
;;;702 /* TI1 Configuration */
;;;703 TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
000054 8923 LDRH r3,[r4,#8]
000056 4632 MOV r2,r6
000058 4629 MOV r1,r5
00005a 4638 MOV r0,r7
00005c f7fff7ff BL TI1_Config
;;;704
;;;705 /* Set the Input Capture Prescaler value */
;;;706 TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
000060 88e1 LDRH r1,[r4,#6]
000062 4638 MOV r0,r7
000064 e8bde8bd POP {r4-r8,lr}
000068 f7fff7ff B.W TIM_SetIC1Prescaler
;;;707 }
;;;708 }
;;;709
ENDP
AREA ||i.TIM_BDTRConfig||, CODE, READONLY, ALIGN=1
TIM_BDTRConfig PROC
;;;721 void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct)
;;;722 {
000000 b530 PUSH {r4,r5,lr}
;;;723 /* Check the parameters */
;;;724 assert_param(IS_TIM_18_PERIPH(TIMx));
;;;725 assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState));
;;;726 assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState));
;;;727 assert_param(IS_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->TIM_LOCKLevel));
;;;728 assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct->TIM_Break));
;;;729 assert_param(IS_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->TIM_BreakPolarity));
;;;730 assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->TIM_AutomaticOutput));
;;;731
;;;732 /* Set the Lock level, the Break enable Bit and the Ploarity, the OSSR State,
;;;733 the OSSI State, the dead time value and the Automatic Output Enable Bit */
;;;734
;;;735 TIMx->BDTR = (u32)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState |
000002 880a LDRH r2,[r1,#0]
000004 884d LDRH r5,[r1,#2]
000006 888b LDRH r3,[r1,#4]
000008 88cc LDRH r4,[r1,#6]
00000a 432a ORRS r2,r2,r5
00000c 4323 ORRS r3,r3,r4
00000e 431a ORRS r2,r2,r3
000010 890d LDRH r5,[r1,#8]
000012 894b LDRH r3,[r1,#0xa]
000014 432a ORRS r2,r2,r5
000016 8989 LDRH r1,[r1,#0xc]
000018 431a ORRS r2,r2,r3
00001a 430a ORRS r2,r2,r1
00001c f8a0f8a0 STRH r2,[r0,#0x44]
;;;736 TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime |
;;;737 TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity |
;;;738 TIM_BDTRInitStruct->TIM_AutomaticOutput;
;;;739
;;;740 }
000020 bd30 POP {r4,r5,pc}
;;;741
ENDP
AREA ||i.TIM_TimeBaseStructInit||, CODE, READONLY, ALIGN=1
TIM_TimeBaseStructInit PROC
;;;752 /* Set the default configuration */
;;;753 TIM_TimeBaseInitStruct->TIM_Period = 0xFFFF;
000000 f64ff64f MOV r1,#0xffff
000004 8081 STRH r1,[r0,#4]
;;;754 TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000;
000006 2100 MOVS r1,#0
000008 8001 STRH r1,[r0,#0]
;;;755 TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1;
00000a 80c1 STRH r1,[r0,#6]
;;;756 TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up;
00000c 8041 STRH r1,[r0,#2]
;;;757 TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000;
00000e 7201 STRB r1,[r0,#8]
;;;758 }
000010 4770 BX lr
;;;759
ENDP
AREA ||i.TIM_OCStructInit||, CODE, READONLY, ALIGN=1
TIM_OCStructInit PROC
;;;770 /* Set the default configuration */
;;;771 TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing;
000000 2100 MOVS r1,#0
000002 8001 STRH r1,[r0,#0]
;;;772 TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable;
000004 8041 STRH r1,[r0,#2]
;;;773 TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable;
000006 8081 STRH r1,[r0,#4]
;;;774 TIM_OCInitStruct->TIM_Pulse = 0x0000;
000008 80c1 STRH r1,[r0,#6]
;;;775 TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High;
00000a 8101 STRH r1,[r0,#8]
;;;776 TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High;
00000c 8141 STRH r1,[r0,#0xa]
;;;777 TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset;
00000e 8181 STRH r1,[r0,#0xc]
;;;778 TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset;
000010 81c1 STRH r1,[r0,#0xe]
;;;779 }
000012 4770 BX lr
;;;780
ENDP
AREA ||i.TIM_ICStructInit||, CODE, READONLY, ALIGN=1
TIM_ICStructInit PROC
;;;791 /* Set the default configuration */
;;;792 TIM_ICInitStruct->TIM_Channel = TIM_Channel_1;
000000 2100 MOVS r1,#0
000002 8001 STRH r1,[r0,#0]
;;;793 TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising;
000004 8041 STRH r1,[r0,#2]
;;;794 TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI;
000006 2201 MOVS r2,#1
000008 8082 STRH r2,[r0,#4]
;;;795 TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1;
00000a 80c1 STRH r1,[r0,#6]
;;;796 TIM_ICInitStruct->TIM_ICFilter = 0x00;
00000c 8101 STRH r1,[r0,#8]
;;;797 }
00000e 4770 BX lr
;;;798
ENDP
AREA ||i.TIM_BDTRStructInit||, CODE, READONLY, ALIGN=1
TIM_BDTRStructInit PROC
;;;809 /* Set the default configuration */
;;;810 TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable;
000000 2100 MOVS r1,#0
000002 8001 STRH r1,[r0,#0]
;;;811 TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable;
000004 8041 STRH r1,[r0,#2]
;;;812 TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF;
000006 8081 STRH r1,[r0,#4]
;;;813 TIM_BDTRInitStruct->TIM_DeadTime = 0x00;
000008 80c1 STRH r1,[r0,#6]
;;;814 TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable;
00000a 8101 STRH r1,[r0,#8]
;;;815 TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low;
00000c 8141 STRH r1,[r0,#0xa]
;;;816 TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable;
00000e 8181 STRH r1,[r0,#0xc]
;;;817 }
000010 4770 BX lr
;;;818
ENDP
AREA ||i.TIM_Cmd||, CODE, READONLY, ALIGN=1
TIM_Cmd PROC
;;;833
;;;834 if (NewState != DISABLE)
000000 2900 CMP r1,#0
;;;835 {
;;;836 /* Enable the TIM Counter */
;;;837 TIMx->CR1 |= CR1_CEN_Set;
000002 8801 LDRH r1,[r0,#0]
000004 d002 BEQ |L19.12|
000006 f041f041 ORR r1,r1,#1
00000a e002 B |L19.18|
|L19.12|
;;;838 }
;;;839 else
;;;840 {
;;;841 /* Disable the TIM Counter */
;;;842 TIMx->CR1 &= CR1_CEN_Reset;
00000c f240f240 MOV r2,#0x3fe
000010 4011 ANDS r1,r1,r2
|L19.18|
000012 8001 STRH r1,[r0,#0] ;837
;;;843 }
;;;844 }
000014 4770 BX lr
;;;845
ENDP
AREA ||i.TIM_CtrlPWMOutputs||, CODE, READONLY, ALIGN=1
TIM_CtrlPWMOutputs PROC
;;;860
;;;861 if (NewState != DISABLE)
000000 2900 CMP r1,#0
;;;862 {
;;;863 /* Enable the TIM Main Output */
;;;864 TIMx->BDTR |= BDTR_MOE_Set;
000002 f830f830 LDRH r1,[r0,#0x44]!
000006 d002 BEQ |L20.14|
000008 f441f441 ORR r1,r1,#0x8000
00000c e001 B |L20.18|
|L20.14|
;;;865 }
;;;866 else
;;;867 {
;;;868 /* Disable the TIM Main Output */
;;;869 TIMx->BDTR &= BDTR_MOE_Reset;
00000e f3c1f3c1 UBFX r1,r1,#0,#15
|L20.18|
000012 8001 STRH r1,[r0,#0] ;864
;;;870 }
;;;871 }
000014 4770 BX lr
;;;872
ENDP
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