📄 stm32f10x_tim.txt
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;;;520 assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
;;;521
;;;522 /* Disable the Channel 2: Reset the CC4E Bit */
;;;523 TIMx->CCER &= CCER_CC4E_Reset;
000002 8c02 LDRH r2,[r0,#0x20]
000004 f422f422 BIC r2,r2,#0x1000
000008 8402 STRH r2,[r0,#0x20]
;;;524
;;;525 /* Get the TIMx CCER register value */
;;;526 tmpccer = TIMx->CCER;
00000a 8c05 LDRH r5,[r0,#0x20]
;;;527
;;;528 /* Get the TIMx CR2 register value */
;;;529 tmpcr2 = TIMx->CR2;
00000c 8882 LDRH r2,[r0,#4]
;;;530
;;;531 /* Get the TIMx CCMR2 register value */
;;;532 tmpccmrx = TIMx->CCMR2;
00000e 8b83 LDRH r3,[r0,#0x1c]
;;;533
;;;534 /* Reset the Output Compare Mode Bits */
;;;535 tmpccmrx &= CCMR_OC24M_Mask;
;;;536
;;;537 /* Select the Output Compare Mode */
;;;538 tmpccmrx |= (u16)(TIM_OCInitStruct->TIM_OCMode << 8);
;;;539
;;;540 /* Reset the Output Polarity level */
;;;541 tmpccer &= CCER_CC4P_Reset;
000010 f425f425 BIC r5,r5,#0x2000
000014 f423f423 BIC r4,r3,#0x7000 ;535
000018 880b LDRH r3,[r1,#0] ;538
;;;542
;;;543 /* Set the Output Compare Polarity */
;;;544 tmpccer |= (u16)(TIM_OCInitStruct->TIM_OCPolarity << 12);
;;;545
;;;546 /* Set the Output State */
;;;547 tmpccer |= (u16)(TIM_OCInitStruct->TIM_OutputState << 12);
;;;548
;;;549 /* Set the Capture Compare Register value */
;;;550 TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse;
;;;551
;;;552 if((*(u32*)&TIMx == TIM1_BASE) || (*(u32*)&TIMx == TIM8_BASE))
00001a 4e0f LDR r6,|L6.88|
00001c 061b LSLS r3,r3,#24 ;538
00001e ea44ea44 ORR r3,r4,r3,LSR #16 ;538
000022 890c LDRH r4,[r1,#8] ;544
000024 0724 LSLS r4,r4,#28 ;544
000026 ea45ea45 ORR r4,r5,r4,LSR #16 ;544
00002a 884d LDRH r5,[r1,#2] ;547
00002c 072d LSLS r5,r5,#28 ;547
00002e ea44ea44 ORR r5,r4,r5,LSR #16 ;547
000032 88cc LDRH r4,[r1,#6] ;550
000034 42b0 CMP r0,r6
000036 f8a0f8a0 STRH r4,[r0,#0x40] ;550
00003a d002 BEQ |L6.66|
00003c 4c07 LDR r4,|L6.92|
00003e 42a0 CMP r0,r4
000040 d105 BNE |L6.78|
|L6.66|
;;;553 {
;;;554 assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
;;;555
;;;556 /* Reset the Ouput Compare IDLE State */
;;;557 tmpcr2 &= CR2_OIS4_Reset;
;;;558
;;;559 /* Set the Output Idle state */
;;;560 tmpcr2 |= (u16)(TIM_OCInitStruct->TIM_OCIdleState << 6);
000042 8989 LDRH r1,[r1,#0xc]
000044 f3c2f3c2 UBFX r4,r2,#0,#14 ;557
000048 0589 LSLS r1,r1,#22
00004a ea44ea44 ORR r2,r4,r1,LSR #16
|L6.78|
;;;561 }
;;;562
;;;563 /* Write to TIMx CR2 */
;;;564 TIMx->CR2 = tmpcr2;
00004e 8082 STRH r2,[r0,#4]
;;;565
;;;566 /* Write to TIMx CCMR2 */
;;;567 TIMx->CCMR2 = tmpccmrx;
000050 8383 STRH r3,[r0,#0x1c]
;;;568
;;;569 /* Write to TIMx CCER */
;;;570 TIMx->CCER = tmpccer;
000052 8405 STRH r5,[r0,#0x20]
;;;571 }
000054 bd70 POP {r4-r6,pc}
;;;572
ENDP
000056 0000 DCW 0x0000
|L6.88|
000058 40012c00 DCD 0x40012c00
|L6.92|
00005c 40013400 DCD 0x40013400
AREA ||i.TIM_SetIC4Prescaler||, CODE, READONLY, ALIGN=1
TIM_SetIC4Prescaler PROC
000000 8b82 LDRH r2,[r0,#0x1c]
000002 f422f422 BIC r2,r2,#0xc00
000006 8382 STRH r2,[r0,#0x1c]
000008 8b82 LDRH r2,[r0,#0x1c]
00000a ea42ea42 ORR r2,r2,r1,LSL #8
00000e 8382 STRH r2,[r0,#0x1c]
000010 4770 BX lr
ENDP
AREA ||i.TIM_SetIC3Prescaler||, CODE, READONLY, ALIGN=1
TIM_SetIC3Prescaler PROC
000000 8b82 LDRH r2,[r0,#0x1c]
000002 f022f022 BIC r2,r2,#0xc
000006 8382 STRH r2,[r0,#0x1c]
000008 8b82 LDRH r2,[r0,#0x1c]
00000a 430a ORRS r2,r2,r1
00000c 8382 STRH r2,[r0,#0x1c]
00000e 4770 BX lr
ENDP
AREA ||i.TIM_SetIC2Prescaler||, CODE, READONLY, ALIGN=1
TIM_SetIC2Prescaler PROC
000000 8b02 LDRH r2,[r0,#0x18]
000002 f422f422 BIC r2,r2,#0xc00
000006 8302 STRH r2,[r0,#0x18]
000008 8b02 LDRH r2,[r0,#0x18]
00000a ea42ea42 ORR r2,r2,r1,LSL #8
00000e 8302 STRH r2,[r0,#0x18]
000010 4770 BX lr
ENDP
AREA ||i.TI2_Config||, CODE, READONLY, ALIGN=1
TI2_Config PROC
;;;3101 u16 TIM_ICFilter)
;;;3102 {
000000 b530 PUSH {r4,r5,lr}
;;;3103 u16 tmpccmr1 = 0, tmpccer = 0, tmp = 0;
;;;3104
;;;3105 /* Disable the Channel 2: Reset the CC2E Bit */
;;;3106 TIMx->CCER &= CCER_CC2E_Reset;
000002 8c04 LDRH r4,[r0,#0x20]
000004 f024f024 BIC r4,r4,#0x10
000008 8404 STRH r4,[r0,#0x20]
;;;3107
;;;3108 tmpccmr1 = TIMx->CCMR1;
00000a 8b05 LDRH r5,[r0,#0x18]
;;;3109 tmpccer = TIMx->CCER;
00000c 8c04 LDRH r4,[r0,#0x20]
;;;3110 tmp = (u16)(TIM_ICPolarity << 4);
;;;3111
;;;3112 /* Select the Input and set the filter */
;;;3113 tmpccmr1 &= CCMR_CC24S_Mask & CCMR_IC24F_Mask;
00000e f425f425 BIC r5,r5,#0xf300
;;;3114 tmpccmr1 |= (u16)(TIM_ICFilter << 12);
000012 ea45ea45 ORR r3,r5,r3,LSL #12
;;;3115 tmpccmr1 |= (u16)(TIM_ICSelection << 8);
000016 ea43ea43 ORR r2,r3,r2,LSL #8
;;;3116
;;;3117 /* Select the Polarity and set the CC2E Bit */
;;;3118 tmpccer &= CCER_CC2P_Reset;
00001a f024f024 BIC r3,r4,#0x20
;;;3119 tmpccer |= tmp | CCER_CC2E_Set;
00001e ea43ea43 ORR r3,r3,r1,LSL #4
000022 f043f043 ORR r1,r3,#0x10
;;;3120
;;;3121 /* Write to TIMx CCMR1 and CCER registers */
;;;3122 TIMx->CCMR1 = tmpccmr1 ;
000026 8302 STRH r2,[r0,#0x18]
;;;3123 TIMx->CCER = tmpccer;
000028 8401 STRH r1,[r0,#0x20]
;;;3124 }
00002a bd30 POP {r4,r5,pc}
;;;3125
ENDP
AREA ||i.TIM_SetIC1Prescaler||, CODE, READONLY, ALIGN=1
TIM_SetIC1Prescaler PROC
000000 8b02 LDRH r2,[r0,#0x18]
000002 f022f022 BIC r2,r2,#0xc
000006 8302 STRH r2,[r0,#0x18]
000008 8b02 LDRH r2,[r0,#0x18]
00000a 430a ORRS r2,r2,r1
00000c 8302 STRH r2,[r0,#0x18]
00000e 4770 BX lr
ENDP
AREA ||i.TIM_ICInit||, CODE, READONLY, ALIGN=1
TIM_ICInit PROC
;;;585 void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
;;;586 {
000000 e92de92d PUSH {r4-r8,lr}
000004 460d MOV r5,r1
000006 4604 MOV r4,r0
;;;587 /* Check the parameters */
;;;588 assert_param(IS_TIM_123458_PERIPH(TIMx));
;;;589 assert_param(IS_TIM_CHANNEL(TIM_ICInitStruct->TIM_Channel));
;;;590 assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity));
;;;591 assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection));
;;;592 assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler));
;;;593 assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter));
;;;594
;;;595 if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
000008 8808 LDRH r0,[r1,#0]
00000a 8849 LDRH r1,[r1,#2]
00000c 88aa LDRH r2,[r5,#4]
00000e 892b LDRH r3,[r5,#8]
000010 b940 CBNZ r0,|L12.36|
;;;596 {
;;;597 /* TI1 Configuration */
;;;598 TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
000012 4620 MOV r0,r4
000014 f7fff7ff BL TI1_Config
;;;599 TIM_ICInitStruct->TIM_ICSelection,
;;;600 TIM_ICInitStruct->TIM_ICFilter);
;;;601
;;;602 /* Set the Input Capture Prescaler value */
;;;603 TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
000018 88e9 LDRH r1,[r5,#6]
00001a 4620 MOV r0,r4
00001c e8bde8bd POP {r4-r8,lr}
000020 f7fff7ff B.W TIM_SetIC1Prescaler
|L12.36|
;;;604 }
;;;605 else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2)
000024 2804 CMP r0,#4
000026 d108 BNE |L12.58|
;;;606 {
;;;607 /* TI2 Configuration */
;;;608 TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
000028 4620 MOV r0,r4
00002a f7fff7ff BL TI2_Config
;;;609 TIM_ICInitStruct->TIM_ICSelection,
;;;610 TIM_ICInitStruct->TIM_ICFilter);
;;;611
;;;612 /* Set the Input Capture Prescaler value */
;;;613 TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
00002e 88e9 LDRH r1,[r5,#6]
000030 4620 MOV r0,r4
000032 e8bde8bd POP {r4-r8,lr}
000036 f7fff7ff B.W TIM_SetIC2Prescaler
|L12.58|
;;;614 }
;;;615 else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3)
00003a 2808 CMP r0,#8
00003c 8c20 LDRH r0,[r4,#0x20]
00003e d117 BNE |L12.112|
000040 f420f420 BIC r0,r0,#0x100
000044 8420 STRH r0,[r4,#0x20]
000046 8ba7 LDRH r7,[r4,#0x1c]
000048 8c26 LDRH r6,[r4,#0x20]
00004a 0208 LSLS r0,r1,#8
00004c f027f027 BIC r1,r7,#0xf3
000050 ea42ea42 ORR r3,r2,r3,LSL #4
000054 430b ORRS r3,r3,r1
000056 f426f426 BIC r1,r6,#0x200
00005a 4301 ORRS r1,r1,r0
00005c f441f441 ORR r0,r1,#0x100
000060 83a3 STRH r3,[r4,#0x1c]
000062 8420 STRH r0,[r4,#0x20]
;;;616 {
;;;617 /* TI3 Configuration */
;;;618 TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
;;;619 TIM_ICInitStruct->TIM_ICSelection,
;;;620 TIM_ICInitStruct->TIM_ICFilter);
;;;621
;;;622 /* Set the Input Capture Prescaler value */
;;;623 TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
000064 88e9 LDRH r1,[r5,#6]
000066 4620 MOV r0,r4
000068 e8bde8bd POP {r4-r8,lr}
00006c f7fff7ff B.W TIM_SetIC3Prescaler
|L12.112|
000070 f420f420 BIC r0,r0,#0x1000
000074 8420 STRH r0,[r4,#0x20]
000076 8ba6 LDRH r6,[r4,#0x1c]
000078 8c20 LDRH r0,[r4,#0x20]
00007a 0212 LSLS r2,r2,#8
00007c f426f426 BIC r6,r6,#0xf300
000080 ea42ea42 ORR r2,r2,r3,LSL #12
000084 f420f420 BIC r0,r0,#0x2000
000088 4332 ORRS r2,r2,r6
00008a ea40ea40 ORR r0,r0,r1,LSL #12
00008e f440f440 ORR r0,r0,#0x1000
000092 83a2 STRH r2,[r4,#0x1c]
000094 8420 STRH r0,[r4,#0x20]
;;;624 }
;;;625 else
;;;626 {
;;;627 /* TI4 Configuration */
;;;628 TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
;;;629 TIM_ICInitStruct->TIM_ICSelection,
;;;630 TIM_ICInitStruct->TIM_ICFilter);
;;;631
;;;632 /* Set the Input Capture Prescaler value */
;;;633 TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
000096 88e9 LDRH r1,[r5,#6]
000098 4620 MOV r0,r4
00009a e8bde8bd POP {r4-r8,lr}
00009e f7fff7ff B.W TIM_SetIC4Prescaler
;;;634 }
;;;635 }
;;;636
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