📄 stm32f10x_tim.txt
字号:
00004a 89ca LDRH r2,[r1,#0xe]
00004c 432e ORRS r6,r6,r5 ;301
00004e 4332 ORRS r2,r2,r6
|L3.80|
;;;305 }
;;;306 /* Write to TIMx CR2 */
;;;307 TIMx->CR2 = tmpcr2;
000050 8082 STRH r2,[r0,#4]
;;;308
;;;309 /* Write to TIMx CCMR1 */
;;;310 TIMx->CCMR1 = tmpccmrx;
000052 8304 STRH r4,[r0,#0x18]
;;;311
;;;312 /* Write to TIMx CCER */
;;;313 TIMx->CCER = tmpccer;
000054 8403 STRH r3,[r0,#0x20]
;;;314 }
000056 bdf0 POP {r4-r7,pc}
;;;315
ENDP
|L3.88|
000058 40012c00 DCD 0x40012c00
|L3.92|
00005c 40013400 DCD 0x40013400
AREA ||i.TIM_OC2Init||, CODE, READONLY, ALIGN=2
TIM_OC2Init PROC
;;;328 void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
;;;329 {
000000 b570 PUSH {r4-r6,lr}
;;;330 u16 tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
;;;331
;;;332 /* Check the parameters */
;;;333 assert_param(IS_TIM_123458_PERIPH(TIMx));
;;;334 assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
;;;335 assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
;;;336 assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
;;;337
;;;338 /* Disable the Channel 2: Reset the CC2E Bit */
;;;339 TIMx->CCER &= CCER_CC2E_Reset;
000002 8c02 LDRH r2,[r0,#0x20]
000004 f022f022 BIC r2,r2,#0x10
000008 8402 STRH r2,[r0,#0x20]
;;;340
;;;341 /* Get the TIMx CCER register value */
;;;342 tmpccer = TIMx->CCER;
00000a 8c02 LDRH r2,[r0,#0x20]
;;;343
;;;344 /* Get the TIMx CR2 register value */
;;;345 tmpcr2 = TIMx->CR2;
00000c 8883 LDRH r3,[r0,#4]
;;;346
;;;347 /* Get the TIMx CCMR1 register value */
;;;348 tmpccmrx = TIMx->CCMR1;
00000e 8b04 LDRH r4,[r0,#0x18]
;;;349
;;;350 /* Reset the Output Compare Mode Bits */
;;;351 tmpccmrx &= CCMR_OC24M_Mask;
;;;352
;;;353 /* Select the Output Compare Mode */
;;;354 tmpccmrx |= (u16)(TIM_OCInitStruct->TIM_OCMode << 8);
;;;355
;;;356 /* Reset the Output Polarity level */
;;;357 tmpccer &= CCER_CC2P_Reset;
000010 f022f022 BIC r2,r2,#0x20
000014 f424f424 BIC r5,r4,#0x7000 ;351
000018 880c LDRH r4,[r1,#0] ;354
;;;358
;;;359 /* Set the Output Compare Polarity */
;;;360 tmpccer |= (u16)(TIM_OCInitStruct->TIM_OCPolarity << 4);
;;;361
;;;362 /* Set the Output State */
;;;363 tmpccer |= (u16)(TIM_OCInitStruct->TIM_OutputState << 4);
;;;364
;;;365 /* Set the Capture Compare Register value */
;;;366 TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse;
;;;367
;;;368 if((*(u32*)&TIMx == TIM1_BASE) || (*(u32*)&TIMx == TIM8_BASE))
00001a 4e16 LDR r6,|L4.116|
00001c 0624 LSLS r4,r4,#24 ;354
00001e ea45ea45 ORR r4,r5,r4,LSR #16 ;354
000022 890d LDRH r5,[r1,#8] ;360
000024 052d LSLS r5,r5,#20 ;360
000026 ea42ea42 ORR r5,r2,r5,LSR #16 ;360
00002a 884a LDRH r2,[r1,#2] ;363
00002c 0512 LSLS r2,r2,#20 ;363
00002e ea45ea45 ORR r2,r5,r2,LSR #16 ;363
000032 88cd LDRH r5,[r1,#6] ;366
000034 42b0 CMP r0,r6
000036 8705 STRH r5,[r0,#0x38] ;366
000038 d002 BEQ |L4.64|
00003a 4d0f LDR r5,|L4.120|
00003c 42a8 CMP r0,r5
00003e d115 BNE |L4.108|
|L4.64|
;;;369 {
;;;370 assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
;;;371 assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
;;;372 assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
;;;373 assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
;;;374
;;;375 /* Reset the Output N Polarity level */
;;;376 tmpccer &= CCER_CC2NP_Reset;
;;;377
;;;378 /* Set the Output N Polarity */
;;;379 tmpccer |= (u16)(TIM_OCInitStruct->TIM_OCNPolarity << 4);
000040 894d LDRH r5,[r1,#0xa]
000042 f022f022 BIC r2,r2,#0x80 ;376
000046 052d LSLS r5,r5,#20
000048 ea42ea42 ORR r5,r2,r5,LSR #16
;;;380
;;;381 /* Reset the Output N State */
;;;382 tmpccer &= CCER_CC2NE_Reset;
;;;383
;;;384 /* Set the Output N State */
;;;385 tmpccer |= (u16)(TIM_OCInitStruct->TIM_OutputNState << 4);
00004c 888a LDRH r2,[r1,#4]
00004e f025f025 BIC r5,r5,#0x40 ;382
000052 0512 LSLS r2,r2,#20
000054 ea45ea45 ORR r2,r5,r2,LSR #16
;;;386
;;;387 /* Reset the Ouput Compare and Output Compare N IDLE State */
;;;388 tmpcr2 &= CR2_OIS2_Reset;
;;;389 tmpcr2 &= CR2_OIS2N_Reset;
;;;390
;;;391 /* Set the Output Idle state */
;;;392 tmpcr2 |= (u16)(TIM_OCInitStruct->TIM_OCIdleState << 2);
000058 898d LDRH r5,[r1,#0xc]
;;;393
;;;394 /* Set the Output N Idle state */
;;;395 tmpcr2 |= (u16)(TIM_OCInitStruct->TIM_OCNIdleState << 2);
00005a 89c9 LDRH r1,[r1,#0xe]
00005c 04ad LSLS r5,r5,#18 ;392
00005e f423f423 BIC r3,r3,#0x8c00 ;389
000062 ea43ea43 ORR r5,r3,r5,LSR #16 ;392
000066 0489 LSLS r1,r1,#18
000068 ea45ea45 ORR r3,r5,r1,LSR #16
|L4.108|
;;;396 }
;;;397
;;;398 /* Write to TIMx CR2 */
;;;399 TIMx->CR2 = tmpcr2;
00006c 8083 STRH r3,[r0,#4]
;;;400
;;;401 /* Write to TIMx CCMR1 */
;;;402 TIMx->CCMR1 = tmpccmrx;
00006e 8304 STRH r4,[r0,#0x18]
;;;403
;;;404 /* Write to TIMx CCER */
;;;405 TIMx->CCER = tmpccer;
000070 8402 STRH r2,[r0,#0x20]
;;;406 }
000072 bd70 POP {r4-r6,pc}
;;;407
ENDP
|L4.116|
000074 40012c00 DCD 0x40012c00
|L4.120|
000078 40013400 DCD 0x40013400
AREA ||i.TIM_OC3Init||, CODE, READONLY, ALIGN=2
TIM_OC3Init PROC
;;;420 void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
;;;421 {
000000 b570 PUSH {r4-r6,lr}
;;;422 u16 tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
;;;423
;;;424 /* Check the parameters */
;;;425 assert_param(IS_TIM_123458_PERIPH(TIMx));
;;;426 assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
;;;427 assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
;;;428 assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
;;;429
;;;430 /* Disable the Channel 2: Reset the CC2E Bit */
;;;431 TIMx->CCER &= CCER_CC3E_Reset;
000002 8c02 LDRH r2,[r0,#0x20]
000004 f422f422 BIC r2,r2,#0x100
000008 8402 STRH r2,[r0,#0x20]
;;;432
;;;433 /* Get the TIMx CCER register value */
;;;434 tmpccer = TIMx->CCER;
00000a 8c05 LDRH r5,[r0,#0x20]
;;;435
;;;436 /* Get the TIMx CR2 register value */
;;;437 tmpcr2 = TIMx->CR2;
00000c 8883 LDRH r3,[r0,#4]
;;;438
;;;439 /* Get the TIMx CCMR2 register value */
;;;440 tmpccmrx = TIMx->CCMR2;
00000e 8b82 LDRH r2,[r0,#0x1c]
;;;441
;;;442 /* Reset the Output Compare Mode Bits */
;;;443 tmpccmrx &= CCMR_OC13M_Mask;
;;;444
;;;445 /* Select the Output Compare Mode */
;;;446 tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
000010 880c LDRH r4,[r1,#0]
000012 f022f022 BIC r2,r2,#0x70 ;443
;;;447
;;;448 /* Reset the Output Polarity level */
;;;449 tmpccer &= CCER_CC3P_Reset;
;;;450
;;;451 /* Set the Output Compare Polarity */
;;;452 tmpccer |= (u16)(TIM_OCInitStruct->TIM_OCPolarity << 8);
000016 890e LDRH r6,[r1,#8]
000018 4314 ORRS r4,r4,r2 ;446
00001a f425f425 BIC r5,r5,#0x200 ;449
00001e 0632 LSLS r2,r6,#24
000020 ea45ea45 ORR r6,r5,r2,LSR #16
;;;453
;;;454 /* Set the Output State */
;;;455 tmpccer |= (u16)(TIM_OCInitStruct->TIM_OutputState << 8);
000024 884a LDRH r2,[r1,#2]
;;;456
;;;457 /* Set the Capture Compare Register value */
;;;458 TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse;
000026 88cd LDRH r5,[r1,#6]
000028 0612 LSLS r2,r2,#24 ;455
00002a ea46ea46 ORR r2,r6,r2,LSR #16 ;455
;;;459
;;;460 if((*(u32*)&TIMx == TIM1_BASE) || (*(u32*)&TIMx == TIM8_BASE))
00002e 4e10 LDR r6,|L5.112|
000030 8785 STRH r5,[r0,#0x3c] ;458
000032 42b0 CMP r0,r6
000034 d002 BEQ |L5.60|
000036 4d0f LDR r5,|L5.116|
000038 42a8 CMP r0,r5
00003a d115 BNE |L5.104|
|L5.60|
;;;461 {
;;;462 assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
;;;463 assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
;;;464 assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
;;;465 assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
;;;466
;;;467 /* Reset the Output N Polarity level */
;;;468 tmpccer &= CCER_CC3NP_Reset;
00003c f422f422 BIC r5,r2,#0x800
;;;469
;;;470 /* Set the Output N Polarity */
;;;471 tmpccer |= (u16)(TIM_OCInitStruct->TIM_OCNPolarity << 8);
000040 894a LDRH r2,[r1,#0xa]
;;;472
;;;473 /* Reset the Output N State */
;;;474 tmpccer &= CCER_CC3NE_Reset;
;;;475
;;;476 /* Set the Output N State */
;;;477 tmpccer |= (u16)(TIM_OCInitStruct->TIM_OutputNState << 8);
;;;478
;;;479 /* Reset the Ouput Compare and Output Compare N IDLE State */
;;;480 tmpcr2 &= CR2_OIS3_Reset;
;;;481 tmpcr2 &= CR2_OIS3N_Reset;
000042 f423f423 BIC r3,r3,#0xb000
000046 0612 LSLS r2,r2,#24 ;471
000048 ea45ea45 ORR r2,r5,r2,LSR #16 ;471
00004c f422f422 BIC r5,r2,#0x400 ;474
000050 888a LDRH r2,[r1,#4] ;477
000052 0612 LSLS r2,r2,#24 ;477
000054 ea45ea45 ORR r2,r5,r2,LSR #16 ;477
;;;482
;;;483 /* Set the Output Idle state */
;;;484 tmpcr2 |= (u16)(TIM_OCInitStruct->TIM_OCIdleState << 4);
000058 898d LDRH r5,[r1,#0xc]
;;;485
;;;486 /* Set the Output N Idle state */
;;;487 tmpcr2 |= (u16)(TIM_OCInitStruct->TIM_OCNIdleState << 4);
00005a 89c9 LDRH r1,[r1,#0xe]
00005c 052d LSLS r5,r5,#20 ;484
00005e ea43ea43 ORR r5,r3,r5,LSR #16 ;484
000062 0509 LSLS r1,r1,#20
000064 ea45ea45 ORR r3,r5,r1,LSR #16
|L5.104|
;;;488 }
;;;489
;;;490 /* Write to TIMx CR2 */
;;;491 TIMx->CR2 = tmpcr2;
000068 8083 STRH r3,[r0,#4]
;;;492
;;;493 /* Write to TIMx CCMR2 */
;;;494 TIMx->CCMR2 = tmpccmrx;
00006a 8384 STRH r4,[r0,#0x1c]
;;;495
;;;496 /* Write to TIMx CCER */
;;;497 TIMx->CCER = tmpccer;
00006c 8402 STRH r2,[r0,#0x20]
;;;498 }
00006e bd70 POP {r4-r6,pc}
;;;499
ENDP
|L5.112|
000070 40012c00 DCD 0x40012c00
|L5.116|
000074 40013400 DCD 0x40013400
AREA ||i.TIM_OC4Init||, CODE, READONLY, ALIGN=2
TIM_OC4Init PROC
;;;512 void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
;;;513 {
000000 b570 PUSH {r4-r6,lr}
;;;514 u16 tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
;;;515
;;;516 /* Check the parameters */
;;;517 assert_param(IS_TIM_123458_PERIPH(TIMx));
;;;518 assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
;;;519 assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -