📄 stm32f10x_tim.txt
字号:
; generated by ARM/Thumb C/C++ Compiler with , RVCT3.1 [Build 934] for uVision
; commandline ArmCC [--split_sections --debug -c --asm --interleave -o.\Obj\stm32f10x_tim.o --depend=.\Obj\stm32f10x_tim.d --device=DARMSTM --apcs=interwork -O3 -I..\..\include -I..\..\..\FWLib\library\inc -I..\..\..\USBLib\library\inc -I..\..\SRAM -I"D:\Program Files\MDK KEIL\ARM\INC\ST\STM32F10x" -D__MICROLIB --omf_browse=.\Obj\stm32f10x_tim.crf ..\..\..\FWLib\library\src\stm32f10x_tim.c]
THUMB
AREA ||i.TIM_DeInit||, CODE, READONLY, ALIGN=2
TIM_DeInit PROC
;;;138
;;;139 switch (*(u32*)&TIMx)
000000 4a2a LDR r2,|L1.172|
000002 b510 PUSH {r4,lr}
000004 1a81 SUBS r1,r0,r2
000006 1513 ASRS r3,r2,#20
000008 14d4 ASRS r4,r2,#19
00000a 4290 CMP r0,r2
00000c d03b BEQ |L1.134|
00000e dc10 BGT |L1.50|
000010 f1b0f1b0 CMP r0,#0x40000000
000014 d022 BEQ |L1.92|
000016 4926 LDR r1,|L1.176|
000018 1840 ADDS r0,r0,r1
00001a d026 BEQ |L1.106|
00001c 4298 CMP r0,r3
00001e d02b BEQ |L1.120|
000020 42a0 CMP r0,r4
000022 d141 BNE |L1.168|
;;;140 {
;;;141 case TIM1_BASE:
;;;142 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE);
;;;143 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE);
;;;144 break;
;;;145
;;;146 case TIM2_BASE:
;;;147 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE);
;;;148 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE);
;;;149 break;
;;;150
;;;151 case TIM3_BASE:
;;;152 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE);
;;;153 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE);
;;;154 break;
;;;155
;;;156 case TIM4_BASE:
;;;157 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE);
;;;158 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE);
;;;159 break;
;;;160
;;;161 case TIM5_BASE:
;;;162 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, ENABLE);
000024 2101 MOVS r1,#1
000026 2008 MOVS r0,#8
000028 f7fff7ff BL RCC_APB1PeriphResetCmd
;;;163 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, DISABLE);
00002c 2100 MOVS r1,#0
00002e 2008 MOVS r0,#8
;;;164 break;
000030 e036 B |L1.160|
|L1.50|
000032 4299 CMP r1,r3 ;139
000034 d02e BEQ |L1.148|
000036 f5b1f5b1 CMP r1,#0x11c00 ;139
00003a d00d BEQ |L1.88|
00003c f5b1f5b1 CMP r1,#0x12400 ;139
000040 d132 BNE |L1.168|
;;;165
;;;166 case TIM6_BASE:
;;;167 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE);
;;;168 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE);
;;;169 break;
;;;170
;;;171 case TIM7_BASE:
;;;172 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE);
;;;173 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE);
;;;174 break;
;;;175
;;;176 case TIM8_BASE:
;;;177 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE);
000042 2101 MOVS r1,#1
000044 034c LSLS r4,r1,#13
|L1.70|
000046 4620 MOV r0,r4
000048 f7fff7ff BL RCC_APB2PeriphResetCmd
;;;178 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, DISABLE);
00004c 4620 MOV r0,r4
00004e e8bde8bd POP {r4,lr}
000052 2100 MOVS r1,#0
000054 f7fff7ff B.W RCC_APB2PeriphResetCmd
|L1.88|
000058 2101 MOVS r1,#1 ;142
00005a e7f4 B |L1.70|
|L1.92|
00005c 2101 MOVS r1,#1 ;147
00005e 4608 MOV r0,r1 ;147
000060 f7fff7ff BL RCC_APB1PeriphResetCmd
000064 2100 MOVS r1,#0 ;148
000066 2001 MOVS r0,#1 ;148
000068 e01a B |L1.160|
|L1.106|
00006a 2101 MOVS r1,#1 ;152
00006c 2002 MOVS r0,#2 ;152
00006e f7fff7ff BL RCC_APB1PeriphResetCmd
000072 2100 MOVS r1,#0 ;153
000074 2002 MOVS r0,#2 ;153
000076 e013 B |L1.160|
|L1.120|
000078 2101 MOVS r1,#1 ;157
00007a 2004 MOVS r0,#4 ;157
00007c f7fff7ff BL RCC_APB1PeriphResetCmd
000080 2100 MOVS r1,#0 ;158
000082 2004 MOVS r0,#4 ;158
000084 e00c B |L1.160|
|L1.134|
000086 2101 MOVS r1,#1 ;167
000088 2010 MOVS r0,#0x10 ;167
00008a f7fff7ff BL RCC_APB1PeriphResetCmd
00008e 2100 MOVS r1,#0 ;168
000090 2010 MOVS r0,#0x10 ;168
000092 e005 B |L1.160|
|L1.148|
000094 2101 MOVS r1,#1 ;172
000096 2020 MOVS r0,#0x20 ;172
000098 f7fff7ff BL RCC_APB1PeriphResetCmd
00009c 2100 MOVS r1,#0 ;173
00009e 2020 MOVS r0,#0x20 ;173
|L1.160|
0000a0 e8bde8bd POP {r4,lr} ;173
0000a4 f7fff7ff B.W RCC_APB1PeriphResetCmd
|L1.168|
;;;179 break;
;;;180
;;;181 default:
;;;182 break;
;;;183 }
;;;184 }
0000a8 bd10 POP {r4,pc}
;;;185
ENDP
0000aa 0000 DCW 0x0000
|L1.172|
0000ac 40001000 DCD 0x40001000
|L1.176|
0000b0 bffffc00 DCD 0xbffffc00
AREA ||i.TIM_TimeBaseInit||, CODE, READONLY, ALIGN=2
TIM_TimeBaseInit PROC
;;;198 void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
;;;199 {
000000 b510 PUSH {r4,lr}
;;;200 /* Check the parameters */
;;;201 assert_param(IS_TIM_123458_PERIPH(TIMx));
;;;202 assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode));
;;;203 assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision));
;;;204
;;;205 /* Select the Counter Mode and set the clock division */
;;;206 TIMx->CR1 &= CR1_CKD_Mask & CR1_CounterMode_Mask;
000002 8802 LDRH r2,[r0,#0]
000004 f002f002 AND r2,r2,#0x8f
000008 8002 STRH r2,[r0,#0]
;;;207 TIMx->CR1 |= (u32)TIM_TimeBaseInitStruct->TIM_ClockDivision |
00000a 88ca LDRH r2,[r1,#6]
00000c 884b LDRH r3,[r1,#2]
00000e 8804 LDRH r4,[r0,#0]
000010 431a ORRS r2,r2,r3
000012 4322 ORRS r2,r2,r4
000014 8002 STRH r2,[r0,#0]
;;;208 TIM_TimeBaseInitStruct->TIM_CounterMode;
;;;209 /* Set the Autoreload value */
;;;210 TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ;
000016 888a LDRH r2,[r1,#4]
;;;211
;;;212 /* Set the Prescaler value */
;;;213 TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler;
;;;214
;;;215 /* Generate an update event to reload the Prescaler value immediatly */
;;;216 TIMx->EGR = TIM_PSCReloadMode_Immediate;
;;;217
;;;218 if (((*(u32*)&TIMx) == TIM1_BASE) || ((*(u32*)&TIMx) == TIM8_BASE))
000018 4c06 LDR r4,|L2.52|
00001a 2301 MOVS r3,#1 ;216
00001c 8582 STRH r2,[r0,#0x2c] ;210
00001e 880a LDRH r2,[r1,#0] ;213
000020 42a0 CMP r0,r4
000022 8502 STRH r2,[r0,#0x28] ;213
000024 8283 STRH r3,[r0,#0x14] ;216
000026 d002 BEQ |L2.46|
000028 4a03 LDR r2,|L2.56|
00002a 4290 CMP r0,r2
00002c d101 BNE |L2.50|
|L2.46|
;;;219 {
;;;220 /* Set the Repetition Counter value */
;;;221 TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter;
00002e 7a09 LDRB r1,[r1,#8]
000030 8601 STRH r1,[r0,#0x30]
|L2.50|
;;;222 }
;;;223 }
000032 bd10 POP {r4,pc}
;;;224
ENDP
|L2.52|
000034 40012c00 DCD 0x40012c00
|L2.56|
000038 40013400 DCD 0x40013400
AREA ||i.TIM_OC1Init||, CODE, READONLY, ALIGN=2
TIM_OC1Init PROC
;;;237 void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
;;;238 {
000000 b5f0 PUSH {r4-r7,lr}
;;;239 u16 tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
;;;240
;;;241 /* Check the parameters */
;;;242 assert_param(IS_TIM_123458_PERIPH(TIMx));
;;;243 assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
;;;244 assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
;;;245 assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
;;;246
;;;247 /* Disable the Channel 1: Reset the CC1E Bit */
;;;248 TIMx->CCER &= CCER_CC1E_Reset;
000002 8c02 LDRH r2,[r0,#0x20]
000004 f022f022 BIC r2,r2,#1
000008 8402 STRH r2,[r0,#0x20]
;;;249
;;;250 /* Get the TIMx CCER register value */
;;;251 tmpccer = TIMx->CCER;
00000a 8c05 LDRH r5,[r0,#0x20]
;;;252
;;;253 /* Get the TIMx CR2 register value */
;;;254 tmpcr2 = TIMx->CR2;
00000c 8882 LDRH r2,[r0,#4]
;;;255
;;;256 /* Get the TIMx CCMR1 register value */
;;;257 tmpccmrx = TIMx->CCMR1;
00000e 8b03 LDRH r3,[r0,#0x18]
;;;258
;;;259 /* Reset the Output Compare Mode Bits */
;;;260 tmpccmrx &= CCMR_OC13M_Mask;
;;;261
;;;262 /* Select the Output Compare Mode */
;;;263 tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
000010 880c LDRH r4,[r1,#0]
000012 f023f023 BIC r3,r3,#0x70 ;260
;;;264
;;;265 /* Reset the Output Polarity level */
;;;266 tmpccer &= CCER_CC1P_Reset;
;;;267
;;;268 /* Set the Output Compare Polarity */
;;;269 tmpccer |= TIM_OCInitStruct->TIM_OCPolarity;
000016 890e LDRH r6,[r1,#8]
000018 f025f025 BIC r5,r5,#2 ;266
00001c 431c ORRS r4,r4,r3 ;263
;;;270
;;;271 /* Set the Output State */
;;;272 tmpccer |= TIM_OCInitStruct->TIM_OutputState;
00001e 884b LDRH r3,[r1,#2]
000020 432e ORRS r6,r6,r5 ;269
;;;273
;;;274 /* Set the Capture Compare Register value */
;;;275 TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse;
000022 88cf LDRH r7,[r1,#6]
;;;276
;;;277 if((*(u32*)&TIMx == TIM1_BASE) || (*(u32*)&TIMx == TIM8_BASE))
000024 4d0c LDR r5,|L3.88|
000026 4333 ORRS r3,r3,r6 ;272
000028 8687 STRH r7,[r0,#0x34] ;275
00002a 42a8 CMP r0,r5
00002c d002 BEQ |L3.52|
00002e 4d0b LDR r5,|L3.92|
000030 42a8 CMP r0,r5
000032 d10d BNE |L3.80|
|L3.52|
;;;278 {
;;;279 assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
;;;280 assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
;;;281 assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
;;;282 assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
;;;283
;;;284 /* Reset the Output N Polarity level */
;;;285 tmpccer &= CCER_CC1NP_Reset;
;;;286
;;;287 /* Set the Output N Polarity */
;;;288 tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity;
000034 894d LDRH r5,[r1,#0xa]
000036 f023f023 BIC r3,r3,#8 ;285
00003a 431d ORRS r5,r5,r3
;;;289
;;;290 /* Reset the Output N State */
;;;291 tmpccer &= CCER_CC1NE_Reset;
00003c f025f025 BIC r6,r5,#4
;;;292
;;;293 /* Set the Output N State */
;;;294 tmpccer |= TIM_OCInitStruct->TIM_OutputNState;
000040 888b LDRH r3,[r1,#4]
;;;295
;;;296 /* Reset the Ouput Compare and Output Compare N IDLE State */
;;;297 tmpcr2 &= CR2_OIS1_Reset;
;;;298 tmpcr2 &= CR2_OIS1N_Reset;
000042 f422f422 BIC r5,r2,#0x8300
000046 4333 ORRS r3,r3,r6 ;294
;;;299
;;;300 /* Set the Output Idle state */
;;;301 tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState;
000048 898e LDRH r6,[r1,#0xc]
;;;302
;;;303 /* Set the Output N Idle state */
;;;304 tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState;
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -