📄 fsmc_nor.txt
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; generated by ARM/Thumb C/C++ Compiler with , RVCT3.1 [Build 934] for uVision
; commandline ArmCC [--split_sections --debug -c --asm --interleave -o.\Obj\fsmc_nor.o --depend=.\Obj\fsmc_nor.d --device=DARMSTM --apcs=interwork -O3 -I..\..\include -I..\..\..\FWLib\library\inc -I..\..\..\USBLib\library\inc -I..\..\SRAM -I"D:\Program Files\MDK KEIL\ARM\INC\ST\STM32F10x" -D__MICROLIB --omf_browse=.\Obj\fsmc_nor.crf ..\..\source\fsmc_nor.c]
THUMB
AREA ||i.FSMC_NOR_Init||, CODE, READONLY, ALIGN=2
FSMC_NOR_Init PROC
;;;45 void FSMC_NOR_Init(void)
;;;46 {
000000 b570 PUSH {r4-r6,lr}
000002 b098 SUB sp,sp,#0x60
;;;47 FSMC_NORSRAMInitTypeDef FSMC_NORSRAMInitStructure;
;;;48 FSMC_NORSRAMTimingInitTypeDef p;
;;;49 GPIO_InitTypeDef GPIO_InitStructure;
;;;50
;;;51 RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOE |
000004 2101 MOVS r1,#1
000006 f44ff44f MOV r0,#0x1e0
00000a f7fff7ff BL RCC_APB2PeriphClockCmd
;;;52 RCC_APB2Periph_GPIOF | RCC_APB2Periph_GPIOG, ENABLE);
;;;53
;;;54 /*-- GPIO Configuration ------------------------------------------------------*/
;;;55 /* NOR Data lines configuration */
;;;56 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_8 | GPIO_Pin_9 |
00000e f24cf24c MOV r0,#0xc703
000012 f8adf8ad STRH r0,[sp,#4]
;;;57 GPIO_Pin_10 | GPIO_Pin_14 | GPIO_Pin_15;
;;;58 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
000016 2018 MOVS r0,#0x18
000018 f88df88d STRB r0,[sp,#7]
;;;59 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00001c 2003 MOVS r0,#3
;;;60 GPIO_Init(GPIOD, &GPIO_InitStructure);
00001e 4c33 LDR r4,|L1.236|
000020 f88df88d STRB r0,[sp,#6] ;59
000024 a901 ADD r1,sp,#4
000026 4620 MOV r0,r4
000028 f7fff7ff BL GPIO_Init
;;;61
;;;62 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 |
00002c f64ff64f MOV r0,#0xff80
;;;63 GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 |
;;;64 GPIO_Pin_14 | GPIO_Pin_15;
;;;65 GPIO_Init(GPIOE, &GPIO_InitStructure);
000030 4d2f LDR r5,|L1.240|
000032 f8adf8ad STRH r0,[sp,#4] ;62
000036 a901 ADD r1,sp,#4
000038 4628 MOV r0,r5
00003a f7fff7ff BL GPIO_Init
;;;66
;;;67 /* NOR Address lines configuration */
;;;68 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 |
00003e f24ff24f MOV r0,#0xf03f
000042 f8adf8ad STRH r0,[sp,#4]
;;;69 GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_12 | GPIO_Pin_13 |
;;;70 GPIO_Pin_14 | GPIO_Pin_15;
;;;71 GPIO_Init(GPIOF, &GPIO_InitStructure);
000046 a901 ADD r1,sp,#4
000048 482a LDR r0,|L1.244|
00004a f7fff7ff BL GPIO_Init
;;;72
;;;73 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 |
00004e 203f MOVS r0,#0x3f
;;;74 GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5;
;;;75 GPIO_Init(GPIOG, &GPIO_InitStructure);
000050 4e29 LDR r6,|L1.248|
000052 f8adf8ad STRH r0,[sp,#4] ;73
000056 a901 ADD r1,sp,#4
000058 4630 MOV r0,r6
00005a f7fff7ff BL GPIO_Init
;;;76
;;;77 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13;
00005e f44ff44f MOV r0,#0x3800
000062 f8adf8ad STRH r0,[sp,#4]
;;;78 GPIO_Init(GPIOD, &GPIO_InitStructure);
000066 a901 ADD r1,sp,#4
000068 4620 MOV r0,r4
00006a f7fff7ff BL GPIO_Init
;;;79
;;;80 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3 | GPIO_Pin_3 | GPIO_Pin_5 | GPIO_Pin_6;
00006e 2068 MOVS r0,#0x68
000070 f8adf8ad STRH r0,[sp,#4]
;;;81 GPIO_Init(GPIOE, &GPIO_InitStructure);
000074 a901 ADD r1,sp,#4
000076 4628 MOV r0,r5
000078 f7fff7ff BL GPIO_Init
;;;82
;;;83 /* NOE and NWE configuration */
;;;84 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4 | GPIO_Pin_5;
00007c 2030 MOVS r0,#0x30
00007e f8adf8ad STRH r0,[sp,#4]
;;;85 GPIO_Init(GPIOD, &GPIO_InitStructure);
000082 a901 ADD r1,sp,#4
000084 4620 MOV r0,r4
000086 f7fff7ff BL GPIO_Init
;;;86
;;;87 /* NE2 configuration */
;;;88 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9;
00008a 1560 ASRS r0,r4,#21
00008c f8adf8ad STRH r0,[sp,#4]
;;;89 GPIO_Init(GPIOG, &GPIO_InitStructure);
000090 a901 ADD r1,sp,#4
000092 4630 MOV r0,r6
000094 f7fff7ff BL GPIO_Init
;;;90
;;;91 /*-- FSMC Configuration ----------------------------------------------------*/
;;;92 p.FSMC_AddressSetupTime = 0x05;
000098 2005 MOVS r0,#5
;;;93 p.FSMC_AddressHoldTime = 0x00;
00009a 9002 STR r0,[sp,#8]
00009c 2000 MOVS r0,#0
;;;94 p.FSMC_DataSetupTime = 0x07;
00009e 2107 MOVS r1,#7
;;;95 p.FSMC_BusTurnAroundDuration = 0x00;
0000a0 e9cde9cd STRD r0,r1,[sp,#0xc]
;;;96 p.FSMC_CLKDivision = 0x00;
0000a4 9005 STR r0,[sp,#0x14]
;;;97 p.FSMC_DataLatency = 0x00;
0000a6 9006 STR r0,[sp,#0x18]
;;;98 p.FSMC_AccessMode = FSMC_AccessMode_B;
0000a8 f04ff04f MOV r1,#0x10000000
;;;99
;;;100 FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2;
0000ac e9cde9cd STRD r0,r1,[sp,#0x1c]
0000b0 2102 MOVS r1,#2
;;;101 FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
;;;102 FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_NOR;
0000b2 e9cde9cd STRD r1,r0,[sp,#0x24]
0000b6 2108 MOVS r1,#8
;;;103 FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
0000b8 910b STR r1,[sp,#0x2c]
0000ba 2110 MOVS r1,#0x10
;;;104 FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
;;;105 FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
0000bc e9cde9cd STRD r1,r0,[sp,#0x30]
;;;106 FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
;;;107 FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
;;;108 FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
0000c0 0209 LSLS r1,r1,#8
0000c2 900e STR r0,[sp,#0x38] ;106
0000c4 900f STR r0,[sp,#0x3c] ;107
;;;109 FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
0000c6 e9cde9cd STRD r0,r1,[sp,#0x40]
;;;110 FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
0000ca 9012 STR r0,[sp,#0x48]
;;;111 FSMC_NORSRAMInitStructure.FSMC_AsyncWait = FSMC_AsyncWait_Disable;
0000cc 9013 STR r0,[sp,#0x4c]
;;;112 FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
0000ce 9014 STR r0,[sp,#0x50]
;;;113 FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
0000d0 9015 STR r0,[sp,#0x54]
0000d2 a802 ADD r0,sp,#8
;;;114 FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
0000d4 9016 STR r0,[sp,#0x58]
;;;115
;;;116 FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);
0000d6 9017 STR r0,[sp,#0x5c]
0000d8 a809 ADD r0,sp,#0x24
0000da f7fff7ff BL FSMC_NORSRAMInit
;;;117
;;;118 /* Enable FSMC Bank1_NOR Bank */
;;;119 FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM2, ENABLE);
0000de 2101 MOVS r1,#1
0000e0 2002 MOVS r0,#2
0000e2 f7fff7ff BL FSMC_NORSRAMCmd
;;;120 }
0000e6 b018 ADD sp,sp,#0x60
0000e8 bd70 POP {r4-r6,pc}
;;;121
ENDP
0000ea 0000 DCW 0x0000
|L1.236|
0000ec 40011400 DCD 0x40011400
|L1.240|
0000f0 40011800 DCD 0x40011800
|L1.244|
0000f4 40011c00 DCD 0x40011c00
|L1.248|
0000f8 40012000 DCD 0x40012000
AREA ||i.FSMC_NOR_ReadID||, CODE, READONLY, ALIGN=2
FSMC_NOR_ReadID PROC
;;;131 {
;;;132 NOR_WRITE(ADDR_SHIFT(0x05555), 0x00AA);
000000 4909 LDR r1,|L2.40|
000002 22aa MOVS r2,#0xaa
000004 800a STRH r2,[r1,#0]
;;;133 NOR_WRITE(ADDR_SHIFT(0x02AAA), 0x0055);
000006 4b09 LDR r3,|L2.44|
000008 2255 MOVS r2,#0x55
00000a f8a3f8a3 STRH r2,[r3,#0x554]
;;;134 NOR_WRITE(ADDR_SHIFT(0x05555), 0x0090);
00000e 2290 MOVS r2,#0x90
000010 800a STRH r2,[r1,#0]
;;;135
;;;136 NOR_ID->Manufacturer_Code = *(vu16 *) ADDR_SHIFT(0x0000);
000012 f04ff04f MOV r1,#0x64000000
000016 880a LDRH r2,[r1,#0]
000018 8002 STRH r2,[r0,#0]
;;;137 NOR_ID->Device_Code1 = *(vu16 *) ADDR_SHIFT(0x0001);
00001a 884a LDRH r2,[r1,#2]
00001c 8042 STRH r2,[r0,#2]
;;;138 NOR_ID->Device_Code2 = *(vu16 *) ADDR_SHIFT(0x000E);
00001e 8b8a LDRH r2,[r1,#0x1c]
000020 8082 STRH r2,[r0,#4]
;;;139 NOR_ID->Device_Code3 = *(vu16 *) ADDR_SHIFT(0x000F);
000022 8bc9 LDRH r1,[r1,#0x1e]
000024 80c1 STRH r1,[r0,#6]
;;;140 }
000026 4770 BX lr
;;;141
ENDP
|L2.40|
000028 6400aaaa DCD 0x6400aaaa
|L2.44|
00002c 64005000 DCD 0x64005000
AREA ||i.FSMC_NOR_GetStatus||, CODE, READONLY, ALIGN=2
FSMC_NOR_GetStatus PROC
;;;355 NOR_Status FSMC_NOR_GetStatus(u32 Timeout)
;;;356 {
000000 e92de92d PUSH {r4-r8,lr}
000004 4604 MOV r4,r0
;;;357 u16 val1 = 0x00, val2 = 0x00;
;;;358 NOR_Status status = NOR_ONGOING;
000006 2601 MOVS r6,#1
;;;359 u32 timeout = Timeout;
000008 4605 MOV r5,r0
00000a 4f1c LDR r7,|L3.124|
;;;360
;;;361 /* Poll on NOR memory Ready/Busy signal ------------------------------------*/
;;;362 while((GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_6) != RESET) && (timeout > 0))
00000c e000 B |L3.16|
|L3.14|
;;;363 {
;;;364 timeout--;
00000e 1e6d SUBS r5,r5,#1
|L3.16|
000010 2140 MOVS r1,#0x40 ;362
000012 4638 MOV r0,r7 ;362
000014 f7fff7ff BL GPIO_ReadInputDataBit
000018 b108 CBZ r0,|L3.30|
00001a 2d00 CMP r5,#0 ;362
00001c d1f7 BNE |L3.14|
|L3.30|
;;;365 }
;;;366
;;;367 timeout = Timeout;
00001e 4625 MOV r5,r4
;;;368
;;;369 while((GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_6) == RESET) && (timeout > 0))
000020 e000 B |L3.36|
|L3.34|
;;;370 {
;;;371 timeout--;
000022 1e6d SUBS r5,r5,#1
|L3.36|
000024 2140 MOVS r1,#0x40 ;369
000026 4638 MOV r0,r7 ;369
000028 f7fff7ff BL GPIO_ReadInputDataBit
00002c b908 CBNZ r0,|L3.50|
00002e 2d00 CMP r5,#0 ;369
000030 d1f7 BNE |L3.34|
|L3.50|
000032 f04ff04f MOV r2,#0x64000000 ;369
000036 e01a B |L3.110|
|L3.56|
;;;372 }
;;;373
;;;374 /* Get the NOR memory operation status -------------------------------------*/
;;;375 while((Timeout != 0x00) && (status != NOR_SUCCESS))
;;;376 {
;;;377 Timeout--;
;;;378
;;;379 /* Read DQ6 and DQ5 */
;;;380 val1 = *(vu16 *)(Bank1_NOR2_ADDR);
000038 8810 LDRH r0,[r2,#0]
00003a 1e64 SUBS r4,r4,#1 ;377
;;;381 val2 = *(vu16 *)(Bank1_NOR2_ADDR);
00003c 8811 LDRH r1,[r2,#0]
;;;382
;;;383 /* If DQ6 did not toggle between the two reads then return NOR_Success */
;;;384 if((val1 & 0x0040) == (val2 & 0x0040))
00003e f000f000 AND r3,r0,#0x40
000042 f001f001 AND r1,r1,#0x40
000046 428b CMP r3,r1
000048 d00a BEQ |L3.96|
;;;385 {
;;;386 return NOR_SUCCESS;
;;;387 }
;;;388
;;;389 if((val1 & 0x0020) != 0x0020)
00004a 0680 LSLS r0,r0,#26
00004c d400 BMI |L3.80|
;;;390 {
;;;391 status = NOR_ONGOING;
00004e 2601 MOVS r6,#1
|L3.80|
;;;392 }
;;;393
;;;394 val1 = *(vu16 *)(Bank1_NOR2_ADDR);
000050 8810 LDRH r0,[r2,#0]
;;;395 val2 = *(vu16 *)(Bank1_NOR2_ADDR);
000052 8811 LDRH r1,[r2,#0]
;;;396
;;;397 if((val1 & 0x0040) == (val2 & 0x0040))
000054 f000f000 AND r3,r0,#0x40
000058 f001f001 AND r1,r1,#0x40
00005c 428b CMP r3,r1
00005e d102 BNE |L3.102|
|L3.96|
;;;398 {
;;;399 return NOR_SUCCESS;
000060 2000 MOVS r0,#0
|L3.98|
;;;400 }
;;;401 else if((val1 & 0x0020) == 0x0020)
;;;402 {
;;;403 return NOR_ERROR;
;;;404 }
;;;405 }
;;;406
;;;407 if(Timeout == 0x00)
;;;408 {
;;;409 status = NOR_TIMEOUT;
;;;410 }
;;;411
;;;412 /* Return the operation status */
;;;413 return (status);
;;;414 }
000062 e8bde8bd POP {r4-r8,pc}
|L3.102|
000066 0680 LSLS r0,r0,#26 ;401
000068 d501 BPL |L3.110|
00006a 2002 MOVS r0,#2 ;403
00006c e7f9 B |L3.98|
|L3.110|
00006e b114 CBZ r4,|L3.118|
000070 2e00 CMP r6,#0 ;375
000072 d1e1 BNE |L3.56|
000074 e000 B |L3.120|
|L3.118|
000076 2603 MOVS r6,#3 ;409
|L3.120|
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