📄 stm32f10x_usart.txt
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000002 b2d2 UXTB r2,r2
000004 8302 STRH r2,[r0,#0x18]
;;;634 /* Set the USART guard time */
;;;635 USARTx->GTPR |= (u16)((u16)USART_GuardTime << 0x08);
000006 8b02 LDRH r2,[r0,#0x18]
000008 ea42ea42 ORR r1,r2,r1,LSL #8
00000c 8301 STRH r1,[r0,#0x18]
;;;636 }
00000e 4770 BX lr
;;;637
ENDP
AREA ||i.USART_SetPrescaler||, CODE, READONLY, ALIGN=1
USART_SetPrescaler PROC
;;;654 /* Clear the USART prescaler */
;;;655 USARTx->GTPR &= GTPR_MSB_Mask;
000000 8b02 LDRH r2,[r0,#0x18]
000002 f402f402 AND r2,r2,#0xff00
000006 8302 STRH r2,[r0,#0x18]
;;;656 /* Set the USART prescaler */
;;;657 USARTx->GTPR |= USART_Prescaler;
000008 8b02 LDRH r2,[r0,#0x18]
00000a 430a ORRS r2,r2,r1
00000c 8302 STRH r2,[r0,#0x18]
;;;658 }
00000e 4770 BX lr
;;;659
ENDP
AREA ||i.USART_SmartCardCmd||, CODE, READONLY, ALIGN=1
USART_SmartCardCmd PROC
;;;676
;;;677 if (NewState != DISABLE)
000000 2900 CMP r1,#0
;;;678 {
;;;679 /* Enable the SC mode by setting the SCEN bit in the CR3 register */
;;;680 USARTx->CR3 |= CR3_SCEN_Set;
000002 8a81 LDRH r1,[r0,#0x14]
000004 d002 BEQ |L19.12|
000006 f041f041 ORR r1,r1,#0x20
00000a e001 B |L19.16|
|L19.12|
;;;681 }
;;;682 else
;;;683 {
;;;684 /* Disable the SC mode by clearing the SCEN bit in the CR3 register */
;;;685 USARTx->CR3 &= CR3_SCEN_Reset;
00000c f021f021 BIC r1,r1,#0x20
|L19.16|
000010 8281 STRH r1,[r0,#0x14] ;680
;;;686 }
;;;687 }
000012 4770 BX lr
;;;688
ENDP
AREA ||i.USART_SmartCardNACKCmd||, CODE, READONLY, ALIGN=1
USART_SmartCardNACKCmd PROC
;;;705
;;;706 if (NewState != DISABLE)
000000 2900 CMP r1,#0
;;;707 {
;;;708 /* Enable the NACK transmission by setting the NACK bit in the CR3 register */
;;;709 USARTx->CR3 |= CR3_NACK_Set;
000002 8a81 LDRH r1,[r0,#0x14]
000004 d002 BEQ |L20.12|
000006 f041f041 ORR r1,r1,#0x10
00000a e001 B |L20.16|
|L20.12|
;;;710 }
;;;711 else
;;;712 {
;;;713 /* Disable the NACK transmission by clearing the NACK bit in the CR3 register */
;;;714 USARTx->CR3 &= CR3_NACK_Reset;
00000c f021f021 BIC r1,r1,#0x10
|L20.16|
000010 8281 STRH r1,[r0,#0x14] ;709
;;;715 }
;;;716 }
000012 4770 BX lr
;;;717
ENDP
AREA ||i.USART_HalfDuplexCmd||, CODE, READONLY, ALIGN=1
USART_HalfDuplexCmd PROC
;;;734
;;;735 if (NewState != DISABLE)
000000 2900 CMP r1,#0
;;;736 {
;;;737 /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */
;;;738 USARTx->CR3 |= CR3_HDSEL_Set;
000002 8a81 LDRH r1,[r0,#0x14]
000004 d002 BEQ |L21.12|
000006 f041f041 ORR r1,r1,#8
00000a e001 B |L21.16|
|L21.12|
;;;739 }
;;;740 else
;;;741 {
;;;742 /* Disable the Half-Duplex mode by clearing the HDSEL bit in the CR3 register */
;;;743 USARTx->CR3 &= CR3_HDSEL_Reset;
00000c f021f021 BIC r1,r1,#8
|L21.16|
000010 8281 STRH r1,[r0,#0x14] ;738
;;;744 }
;;;745 }
000012 4770 BX lr
;;;746
ENDP
AREA ||i.USART_IrDAConfig||, CODE, READONLY, ALIGN=1
USART_IrDAConfig PROC
;;;765
;;;766 USARTx->CR3 &= CR3_IRLP_Mask;
000000 8a82 LDRH r2,[r0,#0x14]
000002 f022f022 BIC r2,r2,#4
000006 8282 STRH r2,[r0,#0x14]
;;;767 USARTx->CR3 |= USART_IrDAMode;
000008 8a82 LDRH r2,[r0,#0x14]
00000a 430a ORRS r2,r2,r1
00000c 8282 STRH r2,[r0,#0x14]
;;;768 }
00000e 4770 BX lr
;;;769
ENDP
AREA ||i.USART_IrDACmd||, CODE, READONLY, ALIGN=1
USART_IrDACmd PROC
;;;786
;;;787 if (NewState != DISABLE)
000000 2900 CMP r1,#0
;;;788 {
;;;789 /* Enable the IrDA mode by setting the IREN bit in the CR3 register */
;;;790 USARTx->CR3 |= CR3_IREN_Set;
000002 8a81 LDRH r1,[r0,#0x14]
000004 d002 BEQ |L23.12|
000006 f041f041 ORR r1,r1,#2
00000a e001 B |L23.16|
|L23.12|
;;;791 }
;;;792 else
;;;793 {
;;;794 /* Disable the IrDA mode by clearing the IREN bit in the CR3 register */
;;;795 USARTx->CR3 &= CR3_IREN_Reset;
00000c f021f021 BIC r1,r1,#2
|L23.16|
000010 8281 STRH r1,[r0,#0x14] ;790
;;;796 }
;;;797 }
000012 4770 BX lr
;;;798
ENDP
AREA ||i.USART_GetFlagStatus||, CODE, READONLY, ALIGN=1
USART_GetFlagStatus PROC
;;;821 FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, u16 USART_FLAG)
;;;822 {
000000 4602 MOV r2,r0
;;;823 FlagStatus bitstatus = RESET;
;;;824
;;;825 /* Check the parameters */
;;;826 assert_param(IS_USART_ALL_PERIPH(USARTx));
;;;827 assert_param(IS_USART_FLAG(USART_FLAG));
;;;828 assert_param(IS_USART_PERIPH_FLAG(USARTx, USART_FLAG)); /* The CTS flag is not available for UART4 and UART5 */
;;;829
;;;830 if ((USARTx->SR & USART_FLAG) != (u16)RESET)
000002 8812 LDRH r2,[r2,#0]
000004 2000 MOVS r0,#0 ;823
000006 420a TST r2,r1
000008 d000 BEQ |L24.12|
;;;831 {
;;;832 bitstatus = SET;
00000a 2001 MOVS r0,#1
|L24.12|
;;;833 }
;;;834 else
;;;835 {
;;;836 bitstatus = RESET;
;;;837 }
;;;838 return bitstatus;
;;;839 }
00000c 4770 BX lr
;;;840
ENDP
AREA ||i.USART_ClearFlag||, CODE, READONLY, ALIGN=1
USART_ClearFlag PROC
;;;873
;;;874 USARTx->SR = (u16)~USART_FLAG;
000000 43c9 MVNS r1,r1
000002 8001 STRH r1,[r0,#0]
;;;875 }
000004 4770 BX lr
;;;876
ENDP
AREA ||i.USART_GetITStatus||, CODE, READONLY, ALIGN=1
USART_GetITStatus PROC
;;;900 ITStatus USART_GetITStatus(USART_TypeDef* USARTx, u16 USART_IT)
;;;901 {
000000 b570 PUSH {r4-r6,lr}
;;;902 u32 bitpos = 0x00, itmask = 0x00, usartreg = 0x00;
;;;903 ITStatus bitstatus = RESET;
;;;904
;;;905 /* Check the parameters */
;;;906 assert_param(IS_USART_ALL_PERIPH(USARTx));
;;;907 assert_param(IS_USART_IT(USART_IT));
;;;908 assert_param(IS_USART_PERIPH_IT(USARTx, USART_IT)); /* The CTS interrupt is not available for UART4 and UART5 */
;;;909
;;;910 /* Get the USART register index */
;;;911 usartreg = (((u8)USART_IT) >> 0x05);
;;;912
;;;913 /* Get the interrupt position */
;;;914 itmask = USART_IT & IT_Mask;
000002 f001f001 AND r5,r1,#0x1f
;;;915
;;;916 itmask = (u32)0x01 << itmask;
000006 2601 MOVS r6,#1
000008 2400 MOVS r4,#0 ;903
00000a f3c1f3c1 UBFX r3,r1,#5,#3 ;911
00000e fa06fa06 LSL r2,r6,r5
;;;917
;;;918 if (usartreg == 0x01) /* The IT is in CR1 register */
000012 2b01 CMP r3,#1
000014 d101 BNE |L26.26|
;;;919 {
;;;920 itmask &= USARTx->CR1;
000016 8983 LDRH r3,[r0,#0xc]
000018 e004 B |L26.36|
|L26.26|
;;;921 }
;;;922 else if (usartreg == 0x02) /* The IT is in CR2 register */
00001a 2b02 CMP r3,#2
00001c d101 BNE |L26.34|
;;;923 {
;;;924 itmask &= USARTx->CR2;
00001e 8a03 LDRH r3,[r0,#0x10]
000020 e000 B |L26.36|
|L26.34|
;;;925 }
;;;926 else /* The IT is in CR3 register */
;;;927 {
;;;928 itmask &= USARTx->CR3;
000022 8a83 LDRH r3,[r0,#0x14]
|L26.36|
;;;929 }
;;;930
;;;931 bitpos = USART_IT >> 0x08;
000024 ea4fea4f LSR r1,r1,#8
;;;932
;;;933 bitpos = (u32)0x01 << bitpos;
;;;934 bitpos &= USARTx->SR;
000028 8800 LDRH r0,[r0,#0]
00002a 4213 TST r3,r2 ;924
00002c fa06fa06 LSL r6,r6,r1 ;933
000030 ea00ea00 AND r0,r0,r6
;;;935
;;;936 if ((itmask != (u16)RESET)&&(bitpos != (u16)RESET))
000034 d001 BEQ |L26.58|
000036 b100 CBZ r0,|L26.58|
;;;937 {
;;;938 bitstatus = SET;
000038 2401 MOVS r4,#1
|L26.58|
;;;939 }
;;;940 else
;;;941 {
;;;942 bitstatus = RESET;
;;;943 }
;;;944
;;;945 return bitstatus;
00003a 4620 MOV r0,r4
;;;946 }
00003c bd70 POP {r4-r6,pc}
;;;947
ENDP
AREA ||i.USART_ClearITPendingBit||, CODE, READONLY, ALIGN=1
USART_ClearITPendingBit PROC
;;;982
;;;983 bitpos = USART_IT >> 0x08;
000000 0a0a LSRS r2,r1,#8
;;;984
;;;985 itmask = (u16)((u16)0x01 << bitpos);
000002 2101 MOVS r1,#1
000004 4091 LSLS r1,r1,r2
;;;986 USARTx->SR = (u16)~itmask;
000006 43c9 MVNS r1,r1
000008 8001 STRH r1,[r0,#0]
;;;987 }
00000a 4770 BX lr
;;;988
ENDP
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