📄 stm32f10x_usart.txt
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AREA ||i.USART_ClockStructInit||, CODE, READONLY, ALIGN=1
USART_ClockStructInit PROC
;;;293 /* USART_ClockInitStruct members default value */
;;;294 USART_ClockInitStruct->USART_Clock = USART_Clock_Disable;
000000 2100 MOVS r1,#0
000002 8001 STRH r1,[r0,#0]
;;;295 USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low;
000004 8041 STRH r1,[r0,#2]
;;;296 USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge;
000006 8081 STRH r1,[r0,#4]
;;;297 USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable;
000008 80c1 STRH r1,[r0,#6]
;;;298 }
00000a 4770 BX lr
;;;299
ENDP
AREA ||i.USART_Cmd||, CODE, READONLY, ALIGN=1
USART_Cmd PROC
;;;316
;;;317 if (NewState != DISABLE)
000000 2900 CMP r1,#0
;;;318 {
;;;319 /* Enable the selected USART by setting the UE bit in the CR1 register */
;;;320 USARTx->CR1 |= CR1_UE_Set;
000002 8981 LDRH r1,[r0,#0xc]
000004 d002 BEQ |L6.12|
000006 f441f441 ORR r1,r1,#0x2000
00000a e001 B |L6.16|
|L6.12|
;;;321 }
;;;322 else
;;;323 {
;;;324 /* Disable the selected USART by clearing the UE bit in the CR1 register */
;;;325 USARTx->CR1 &= CR1_UE_Reset;
00000c f421f421 BIC r1,r1,#0x2000
|L6.16|
000010 8181 STRH r1,[r0,#0xc] ;320
;;;326 }
;;;327 }
000012 4770 BX lr
;;;328
ENDP
AREA ||i.USART_ITConfig||, CODE, READONLY, ALIGN=1
USART_ITConfig PROC
;;;354 void USART_ITConfig(USART_TypeDef* USARTx, u16 USART_IT, FunctionalState NewState)
;;;355 {
000000 b510 PUSH {r4,lr}
;;;356 u32 usartreg = 0x00, itpos = 0x00, itmask = 0x00;
;;;357 u32 usartxbase = 0x00;
;;;358
;;;359 /* Check the parameters */
;;;360 assert_param(IS_USART_ALL_PERIPH(USARTx));
;;;361 assert_param(IS_USART_CONFIG_IT(USART_IT));
;;;362 assert_param(IS_USART_PERIPH_IT(USARTx, USART_IT)); /* The CTS interrupt is not available for UART4 and UART5 */
;;;363 assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;364
;;;365 usartxbase = (*(u32*)&(USARTx));
;;;366
;;;367 /* Get the USART register index */
;;;368 usartreg = (((u8)USART_IT) >> 0x05);
000002 f3c1f3c1 UBFX r3,r1,#5,#3
;;;369
;;;370 /* Get the interrupt position */
;;;371 itpos = USART_IT & IT_Mask;
000006 f001f001 AND r4,r1,#0x1f
;;;372
;;;373 itmask = (((u32)0x01) << itpos);
00000a 2101 MOVS r1,#1
00000c 40a1 LSLS r1,r1,r4
;;;374
;;;375 if (usartreg == 0x01) /* The IT is in CR1 register */
00000e 2b01 CMP r3,#1
000010 d101 BNE |L7.22|
;;;376 {
;;;377 usartxbase += 0x0C;
000012 300c ADDS r0,r0,#0xc
000014 e004 B |L7.32|
|L7.22|
;;;378 }
;;;379 else if (usartreg == 0x02) /* The IT is in CR2 register */
000016 2b02 CMP r3,#2
000018 d101 BNE |L7.30|
;;;380 {
;;;381 usartxbase += 0x10;
00001a 3010 ADDS r0,r0,#0x10
00001c e000 B |L7.32|
|L7.30|
;;;382 }
;;;383 else /* The IT is in CR3 register */
;;;384 {
;;;385 usartxbase += 0x14;
00001e 3014 ADDS r0,r0,#0x14
|L7.32|
;;;386 }
;;;387 if (NewState != DISABLE)
000020 2a00 CMP r2,#0
;;;388 {
;;;389 *(vu32*)usartxbase |= itmask;
000022 6802 LDR r2,[r0,#0]
000024 d001 BEQ |L7.42|
000026 430a ORRS r2,r2,r1
000028 e000 B |L7.44|
|L7.42|
;;;390 }
;;;391 else
;;;392 {
;;;393 *(vu32*)usartxbase &= ~itmask;
00002a 438a BICS r2,r2,r1
|L7.44|
00002c 6002 STR r2,[r0,#0] ;389
;;;394 }
;;;395 }
00002e bd10 POP {r4,pc}
;;;396
ENDP
AREA ||i.USART_DMACmd||, CODE, READONLY, ALIGN=1
USART_DMACmd PROC
;;;419
;;;420 if (NewState != DISABLE)
000000 2a00 CMP r2,#0
;;;421 {
;;;422 /* Enable the DMA transfer for selected requests by setting the DMAT and/or
;;;423 DMAR bits in the USART CR3 register */
;;;424 USARTx->CR3 |= USART_DMAReq;
000002 8a82 LDRH r2,[r0,#0x14]
000004 d001 BEQ |L8.10|
000006 430a ORRS r2,r2,r1
000008 e000 B |L8.12|
|L8.10|
;;;425 }
;;;426 else
;;;427 {
;;;428 /* Disable the DMA transfer for selected requests by clearing the DMAT and/or
;;;429 DMAR bits in the USART CR3 register */
;;;430 USARTx->CR3 &= (u16)~USART_DMAReq;
00000a 438a BICS r2,r2,r1
|L8.12|
00000c 8282 STRH r2,[r0,#0x14] ;424
;;;431 }
;;;432 }
00000e 4770 BX lr
;;;433
ENDP
AREA ||i.USART_SetAddress||, CODE, READONLY, ALIGN=1
USART_SetAddress PROC
;;;450 /* Clear the USART address */
;;;451 USARTx->CR2 &= CR2_Address_Mask;
000000 8a02 LDRH r2,[r0,#0x10]
000002 f022f022 BIC r2,r2,#0xf
000006 8202 STRH r2,[r0,#0x10]
;;;452 /* Set the USART address node */
;;;453 USARTx->CR2 |= USART_Address;
000008 8a02 LDRH r2,[r0,#0x10]
00000a 430a ORRS r2,r2,r1
00000c 8202 STRH r2,[r0,#0x10]
;;;454 }
00000e 4770 BX lr
;;;455
ENDP
AREA ||i.USART_WakeUpConfig||, CODE, READONLY, ALIGN=1
USART_WakeUpConfig PROC
;;;474
;;;475 USARTx->CR1 &= CR1_WAKE_Mask;
000000 8982 LDRH r2,[r0,#0xc]
000002 f422f422 BIC r2,r2,#0x800
000006 8182 STRH r2,[r0,#0xc]
;;;476 USARTx->CR1 |= USART_WakeUp;
000008 8982 LDRH r2,[r0,#0xc]
00000a 430a ORRS r2,r2,r1
00000c 8182 STRH r2,[r0,#0xc]
;;;477 }
00000e 4770 BX lr
;;;478
ENDP
AREA ||i.USART_ReceiverWakeUpCmd||, CODE, READONLY, ALIGN=1
USART_ReceiverWakeUpCmd PROC
;;;495
;;;496 if (NewState != DISABLE)
000000 2900 CMP r1,#0
;;;497 {
;;;498 /* Enable the USART mute mode by setting the RWU bit in the CR1 register */
;;;499 USARTx->CR1 |= CR1_RWU_Set;
000002 8981 LDRH r1,[r0,#0xc]
000004 d002 BEQ |L11.12|
000006 f041f041 ORR r1,r1,#2
00000a e001 B |L11.16|
|L11.12|
;;;500 }
;;;501 else
;;;502 {
;;;503 /* Disable the USART mute mode by clearing the RWU bit in the CR1 register */
;;;504 USARTx->CR1 &= CR1_RWU_Reset;
00000c f021f021 BIC r1,r1,#2
|L11.16|
000010 8181 STRH r1,[r0,#0xc] ;499
;;;505 }
;;;506 }
000012 4770 BX lr
;;;507
ENDP
AREA ||i.USART_LINBreakDetectLengthConfig||, CODE, READONLY, ALIGN=1
USART_LINBreakDetectLengthConfig PROC
;;;527
;;;528 USARTx->CR2 &= CR2_LBDL_Mask;
000000 8a02 LDRH r2,[r0,#0x10]
000002 f022f022 BIC r2,r2,#0x20
000006 8202 STRH r2,[r0,#0x10]
;;;529 USARTx->CR2 |= USART_LINBreakDetectLength;
000008 8a02 LDRH r2,[r0,#0x10]
00000a 430a ORRS r2,r2,r1
00000c 8202 STRH r2,[r0,#0x10]
;;;530 }
00000e 4770 BX lr
;;;531
ENDP
AREA ||i.USART_LINCmd||, CODE, READONLY, ALIGN=1
USART_LINCmd PROC
;;;548
;;;549 if (NewState != DISABLE)
000000 2900 CMP r1,#0
;;;550 {
;;;551 /* Enable the LIN mode by setting the LINEN bit in the CR2 register */
;;;552 USARTx->CR2 |= CR2_LINEN_Set;
000002 8a01 LDRH r1,[r0,#0x10]
000004 d002 BEQ |L13.12|
000006 f441f441 ORR r1,r1,#0x4000
00000a e001 B |L13.16|
|L13.12|
;;;553 }
;;;554 else
;;;555 {
;;;556 /* Disable the LIN mode by clearing the LINEN bit in the CR2 register */
;;;557 USARTx->CR2 &= CR2_LINEN_Reset;
00000c f421f421 BIC r1,r1,#0x4000
|L13.16|
000010 8201 STRH r1,[r0,#0x10] ;552
;;;558 }
;;;559 }
000012 4770 BX lr
;;;560
ENDP
AREA ||i.USART_SendData||, CODE, READONLY, ALIGN=1
USART_SendData PROC
;;;577 /* Transmit Data */
;;;578 USARTx->DR = (Data & (u16)0x01FF);
000000 f3c1f3c1 UBFX r1,r1,#0,#9
000004 8081 STRH r1,[r0,#4]
;;;579 }
000006 4770 BX lr
;;;580
ENDP
AREA ||i.USART_ReceiveData||, CODE, READONLY, ALIGN=1
USART_ReceiveData PROC
;;;595 /* Receive Data */
;;;596 return (u16)(USARTx->DR & (u16)0x01FF);
000000 8880 LDRH r0,[r0,#4]
000002 f3c0f3c0 UBFX r0,r0,#0,#9
;;;597 }
000006 4770 BX lr
;;;598
ENDP
AREA ||i.USART_SendBreak||, CODE, READONLY, ALIGN=1
USART_SendBreak PROC
;;;613 /* Send break characters */
;;;614 USARTx->CR1 |= CR1_SBK_Set;
000000 8981 LDRH r1,[r0,#0xc]
000002 f041f041 ORR r1,r1,#1
000006 8181 STRH r1,[r0,#0xc]
;;;615 }
000008 4770 BX lr
;;;616
ENDP
AREA ||i.USART_SetGuardTime||, CODE, READONLY, ALIGN=1
USART_SetGuardTime PROC
;;;632 /* Clear the USART Guard time */
;;;633 USARTx->GTPR &= GTPR_LSB_Mask;
000000 8b02 LDRH r2,[r0,#0x18]
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